標題: | 基於增強和高效的離散餘弦變換的熱模型的構建及其應用於熱感知擺放 Enhanced and Efficient DCT Based Thermal Model Construction and Its Application to Thermal-Aware Placement |
作者: | 吳永證 Suradeth Aroonsantidecha 陳宏明 電子研究所 |
關鍵字: | 熱感知放置;Thermal Aware Placement |
公開日期: | 2011 |
摘要: | 在這篇論文中,我們提出了一種快速、準確的熱感知解析式擺置器(Thermal-Aware Analytical Placer)。熱模型(Thermal model)是以格林函數(Green Function)建構,並以增強的離散餘旋變換(Enhanced-DCT)來產生完整晶片的溫度曲線(Full-Chip Temperature Profile)。與以往其他的熱感知擺置器相比,我們的熱模型與力平衡擺置器緊密地結合。我們提出基於二維高斯模型(2D Gaussian model)的熱散播力(Thermal Spreading Force)以及動態熱區域控制,以降低最高晶片溫度,能優化總半周長(HPWL)和晶片上的溫度分佈。
我們的熱模型已被最新的商業工具驗證,平均偏差在6.5%內,並加速240倍。比起Capo與APlace2,我們的擺置器可以加速3-4倍並達到同樣的結果。實驗是以ISPD2005年的測資(Test Bench)測試,基準高達200萬邏輯閘的設計。其結果更進一步以GSRC計算器評估總HPWL,並用商用軟體ICEPAK做溫度分佈。 In this thesis, we proposed a fast and accurate thermal aware analytical placer. Thermal model is constructed based on Green function with enhanced DCT to generate full chip temperature profile. Unlike other previous thermal aware placers, our thermal model is tightly integrated with a flat force directed placement. A thermal spreading force based on 2D Gaussian model is proposed to reduce maximum on-chip temperature with dynamic hot region size control, optimizing between total half-perimeter wirelength (HPWL) and on-chip temperature distribution. Our thermal model is verified by the most recent commercial tool and has an average deviation within 6.5% with 240x speed up. Our placer can reach the same quality compared to Capo and APlace2 with 3-4x speed up. Experiments are tested using ISPD 2005 benchmark with up to 2 million gate design. The results are further evaluated using GSRC Bookshelf Evaluator for total HPWL, and using ICEPAK for temperature distribution. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079811625 http://hdl.handle.net/11536/46790 |
顯示於類別: | 畢業論文 |