具有面積效率及可重組多模式和多訊號流快速濾波演算法濾波器設計

Abstract

本篇論文主要提出了一種可重組多模式和多訊號流的平行濾波器架構設計，這是一個可以根據不同通訊標準的傳輸率來重組出適合其平行度的濾波器架構將可適用於軟體無線電之前端通訊平台設計。濾波器的平行運算是將輸入訊號和濾波器拆解成多個次訊號並利用次濾波器之間的運算共享降低計算每一點濾波器輸出的運算量。有限脈衝響應(Finite Impulse Response，FIR)濾波器的線性相角係數對稱的特性可以用來減少係數長度一半的乘法量，然而此對稱性在濾波器的平行運算中原始濾波器被拆解成多個小的組合濾波器時有可能會被破壞，因此如何在平行化濾波器中擁有最多對稱係數的次濾波器是一個可研究的議題。我們在論文中結合了兩種現有的平行濾波演算法提出了新的具有面積效率且可支援多階數的平行濾波器演算法和架構，再結合[30]中的快速濾波演算法可降低提出方法在演算法部分的運算複雜度，比起Duhamel所提出的傳統平行濾波演算法[1]最多可減少約50%的乘法量而其代價為55%的加法增加量。以直接對應所提出演算法的方式實現硬體的複雜度與[2]的架構相比，提出架構可有效節省約10%的硬體面積。 論文中以所提出之可重組平行濾波器架構實做可用於IEEE 802.15.3c、IEEE 802.11ad、IEEE 802.11ac及LTE等多標準的前端濾波器，依據不同標準所提出之架構可重組出各標準所需之係數且可依其資料率重組為適當平行度之架構，與Duhamel提出的平行濾波演算法[1]相比在這個案例中結合[30]的快速濾波演算法所減少的運算複雜度為 45%的乘法減少量而代價為55%的加法增加量。以Verilog硬體描述語言並使用聯電90nm製程合成硬體面積70215 、功率23.5 ，時脈率(clock rate)可達2.64 的SDR濾波器也實現於本文中。

In this thesis, reconfigurable multi-mode and multi-stream parallel filter architectures for the front-end filtering operations of software-defined radio are proposed. The architectures can flexibly configure their hardware components to meet different kinds of communication specifications. It is well-known that one can reduce the complexity of a convolution operation, by reformulating the convolution equation into several parallel multi-output convolution equations composed by many smaller sub-filterings. By doing this way, some computation redundancy can be removed. Furthermore, one can utilize the symmetry feature of linear-phase FIR filters to save about half amount of multiplication operations. However, the symmetry property of the original filter may be destroyed after the aforementioned parallel decomposition process. How to obtain the subfilters with symmetric coefficients as much as possible in the parallel decomposition process is highly desirable. The thesis is aimed to achieve the design goal. Specifically, this thesis proposes new area-efficient FIR filter structures which apply to any FIR filter types with high-degree symmetry in subfilters. Furthermore, by combining the algorithm in [30], the proposed design can achieve up to 50% reduction in multiplication counts, at the cost of about 55% increase in addition operations compared to the Duhamel’s algorithm in [1]. Using the direct mapping method to implement the hardware，the proposed structures can save about 10% hardware area compared to the structures in [2]. The SDR front-end filter based on the proposed reconfigurable parallel filter architectures and the reconfigurable multiplier blocks for IEEE 802.15.3c, IEEE 802.11ad, IEEE 802.11ac and LTE systems are also implemented. For the specific design, the proposed structure can achieve about 45% reduction in multiplication counts, at the cost of about 55% increase in addition operations compared to the Duhamel’s algorithm in [30] by combining the proposed structures with the algorithms in [30]. The CAD synthesis result with UMC 90nm technologies shows that the SDR front-end filter has an area of 70215 , of power 23.5 at the clock rate of 2.64 .