1.5億位元時脈與資料回復電路

Abstract

近年來，隨著互補式金氧半製程技術的發展，以及處理器運算能力的快速提升，顯示出用以傳輸資訊的寬頻資料連結越來越趨重要。在許多應用中，比如電腦內部、電腦與電腦間和電腦與周邊間的界面，這樣的連結通常是一個很重要的部分，也是目前整體系統操作速度的瓶頸。為了克服在資料傳輸過程中由各種雜訊源所導致的訊號完整性問題，接收器在整個高速連結效能的表現中扮演了一個重要的角色，而其中最複雜的部分之一就是時脈與資料回復電路的設計。如何利用互補式金氧半製程設計出一高速、低功率消耗、低成本與高度整合性的時脈與資料回復電路也就成為複雜且具有挑戰性的考量。 本論文所提出的1.5億位元時脈與資料回復電路具有半速率Bang Bang相位偵測器與頻率追蹤器，在Bang Bang相位偵測器與電壓至電流轉換器之間加入了電壓位準轉換電路，把原本電流模式邏輯閘(Current Mode Logic Gate)的小擺幅轉換為全擺幅，因此電壓至電流轉換器之輸入端可視為開關，一次充放固定電流，使整個迴路更穩定。此外壓控振盪器(VCO)的兩個振盪頻帶，搭配所提出的頻帶切換控制電路，使整個迴路的鎖定範圍增加，確保在製程及環境變異下仍能鎖定目標頻率。 本論文所呈現之晶片使用台積電所提供之0.35微米2P4M以及0.18微米3.3V 1P6M的標準互補式金氧半製程來完成。

In recent years, the scaling of CMOS process technologies and the increasing computational capability of processors show that high bandwidth links to communicate information are getting more and more important. Such high speed links are necessary parts of many applications, such as inner computer, computer-to-computer, or computer-to-peripheral interfaces, and they are also the bottleneck of the system operating speed. To overcome the signal integrity problems induced by various noise sources during data, the receiver design plays an important role in the overall performance of high speed links. The design of clock and data recovery(CDR) circuits is one of the most complicated parts of the transceiver implementation. How to apply CMOS process to design a high-speed, low power consumption, low cost and highly integrated clock and data recovery circuit has become complicated and challenging considerations. This paper proposes a 1.5Gb/s CDR with a half rate bang bang phase detector and frequency tracing circuit, a voltage to current converter (V/I converter) inserted between them, converting the original small swing of current mode logic gates to full swing. Therefore, the input of V/I converter can be viewed as switches, charging or discharging fixed current at one time, making the loop become more stable. Besides, the two oscillation bands of the VCO, along with the proposed band hop control circuit, make the locking range of the whole loop increase and ensure the lock of the target frequency despite the variation of the process and environment. The proposed chips were fabricated by standard TSMC 0.35μm 2P4M and TSMC 0.18um 3.3V 1P6M CMOS processes.