| 標題: | CORRELATIONS BETWEEN CMOS LATCH-UP CHARACTERISTICS AND SUBSTRATE STRUCTURE PARAMETERS |
| 作者: | CHEN, MJ WU, CY 交大名義發表 工學院 National Chiao Tung University College of Engineering |
| 公開日期: | 1-Oct-1986 |
| URI: | http://hdl.handle.net/11536/4721 |
| ISSN: | 0038-1101 |
| 期刊: | SOLID-STATE ELECTRONICS |
| Volume: | 29 |
| Issue: | 10 |
| 起始頁: | 1079 |
| 結束頁: | 1086 |
| Appears in Collections: | Articles |
- A physical model for the correlation between holding voltage and holding current in epitaxial CMOS latch-up / Chen, MJ;Lee, HS;Chen, JH;Hou, CS;Lin, CS
- 次微米互補式金氧半鎖定及基座偏壓產生器 / 周業輝;Yeh-Huei Jou;陳明哲;Ming-Jer Chen
- 次微米互補式金氧半鎖定及基座偏壓產生器 / 周業甯;Jou, Yeh-Ning;陳明哲;Chen, Ming-Jer
- Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations / Ker, Ming-Dou;Hsu, Sheng-Fu
- TIMING MACROMODELS FOR CMOS STATIC SET RESET LATCHES AND THEIR APPLICATIONS / WU, CY;LI, C;HWANG, JS
- Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process / Ker, MD;Hsu, KC
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