完整後設資料紀錄
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dc.contributor.author王韋傑en_US
dc.contributor.authorWang, Wei-Chiehen_US
dc.contributor.author張翼en_US
dc.contributor.authorChang, Yien_US
dc.date.accessioned2014-12-12T01:49:01Z-
dc.date.available2014-12-12T01:49:01Z-
dc.date.issued2011en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#GT079818554en_US
dc.identifier.urihttp://hdl.handle.net/11536/47381-
dc.description.abstract本研究論文以變溫砷介面層(300~420 °C)成長砷化鎵磊晶層於矽/鍺基板上。由實驗結果證實,變溫砷介面層成長在經由650 °C退火後矽/鍺基板不僅可有效改善隨後成長之砷化鎵磊晶層表面形貌(Rms: 1.1 nm)亦可減少反向疇(APDs)產生,使砷化鎵磊晶層缺陷密度降低至2 × 107 cm-2。由於變溫砷介面層中砷原子與矽/鍺基板中鍺原子間鍵結能(bonding energy)較弱及低五三比(V/III: 20)的使用,使砷化鎵磊晶層與鍺磊晶層間不必要的原子擴散現象被有效抑制。這些研究成果皆證實變溫砷介面層對欲成長於矽基板上之三五族奈米電子元件及光電元件將具有極大的發展潛力。zh_TW
dc.description.abstractThe growth of GaAs epitaxy on Ge/Si substrates with an arsenic prelayer grown with graded temperature ramped from 300 to 420 °C is investigated. It is demonstrated that the graded-temperature arsenic prelayer grown on a Ge/Si substrate annealed at 650 °C not only improves the surface morphology (roughness: 1.1 nm) but also reduces the anti-phase domains’ (APDs) density in GaAs epitaxy (dislocation density: ~2 × 107 cm-2). Moreover, the unwanted interdiffusion between Ge and GaAs epitaxy is suppressed by using the graded-temperature arsenic prelayer due to the low energy of the Ge-As bond and the use of a low V/III ratio of 20. These results suggest that the graded-temperature As prelayer grown on Ge/Si substrate has great potential for use in the growth of III-V nanoelectronic devices and optoelectronic devices on the Si substrate.en_US
dc.language.isoen_USen_US
dc.subject砷化鎵/鍺zh_TW
dc.subject反相邊界zh_TW
dc.subject反相疇zh_TW
dc.subject砷界面層zh_TW
dc.subjectGaAs/Geen_US
dc.subjectantiphase boundariesen_US
dc.subjectantiphase domainsen_US
dc.subjectAs prelayeren_US
dc.title使用變溫砷介面層以成長砷化鎵磊晶層於鍺/矽基板上對三五族太陽能電池之應用zh_TW
dc.titleGrowth of GaAs epitaxy on Ge/Si substrate using graded-temperature arsenic prelayer for III-V solar cells applicationen_US
dc.typeThesisen_US
dc.contributor.department材料科學與工程學系zh_TW
顯示於類別:畢業論文