經由微波退火形成極薄且均勻厚度的鎳矽化物研究

Abstract

近來，國際半導體科技走勢圖(ITRS)對金屬矽化物的厚度預估已達到下修瓶頸，故本論文主要探討在室溫下以物理氣相沉積15奈米(nm)的鎳金屬在矽基板上，再以低溫微波形成金屬矽化物層(Ni Silicide layer)，進而採用兩段式退火方式形成擁有低片電阻值、極薄且均勻厚度的鎳矽化物，以提前符合2012-2021的半導體架構需求。第一階段的退火是利用低功率的微波退火進行，它會促進鎳金屬擴散進入矽基板中。接著在去除未反應的金屬後，再進行第二次的微波退火，藉此以降低片電阻和晶相的轉換。此外，在微波腔體內分別以不同的擺放方式和數量置入石英片和矽晶片，亦會得到不同厚度、阻值和晶相的鎳矽化物，其機制將會在本篇論文裡詳細闡述。第二次退火透過最佳化的擺設方式和功率調整，我們所形成的鎳矽化物的厚度僅從9奈米增加到10.5奈米，而其片電阻值從170歐姆/□降至18歐姆/□。 除此之外，我們也在矽基板上透過超高真空化學氣相沉積方式磊晶一層約200奈米的純鍺，之後運用以上的技術做出一層鎳鍺化物(Ni Germanide layer)，其特性亦會在本論文中詳細描述。 另外，我們也將此微波退火的技術整合在九十奈米的場效電晶體元件的製程上，其汲極電流和漏電流都因此獲得顯著的改善。

For the recent years, ITRS has encountered bottlenecks for predicting the downscaled thickness of nickel silicide (NiSi); therefore in this thesis, we investigated low temperature formation of Ni Silicide layer by physical chemical deposition(PVD) in room temoerature of a 15nm Ni layer on (100) Si substrate.. The formation of ultrathin, homogenoues and low sheet resistance (Rs) Ni silicide film was formed by two-step annealing in order to meet the specifications of 2012-2021 single and multi-gate MPU/ASIC required by ITRS 2010. The first step is applying the low power microwave annealing, which promotes Ni diffusion through a thin interfacial amorphous layer. Then the unreacted metal will be lifted off after first step is finished. The second step annealing is applied in order to lower sheet resistance and firmly merge the phase. Furthermore, inserting quartz and Si suscpetors upon/below the primary wafer with different setups and quantities will also result in different thickness, Rs and phase. Its mechanism will be detailed in this thesis as well. The optimized 2nd step MWA is the key to reduce the Ni-silicide sheet resistance to a record low 18 ohm/sq. from 170 ohm/square (ohm/sq.) while Ni silicide thickness is just slightly increased from 9 nm to 10.5 nm. In addition, we deposited a 2000~3000nm Germanium (Ge) layer upon (100) Si substrate by ultrahigh vacuum chemical vapor deposition (UHVCVD) in order to form the nickel germanide (NiGe) through aforementioned process techniques. Its characteristics will be further discussed in this thesis as well. Besides, we have microwave annealing integrated into 90nm Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) fabrication process. The drain current and leakage are both improved by this novel annealing techniques.