圖形著色器之低耗能編譯器最佳化方法

Abstract

嵌入式系統在現代科技的應用已越來越普遍，各式手持裝置都可見其蹤影，體積小、重量輕、提供特定功能是其特色，然而體積及重量的特性，限制了嵌入式系統上的電源供應，如何對有限的電源做最有效的利用，是嵌入式系統設計一個重要的議題。 Shader Core是建構在圖形處理器（GPU）上的子核心，其主要功能為處理ESSL（OpenGL ES Shading Language）指令，此處圖形處理器指的是整個OpenGL嵌入式系統，Shader Core未來將應用於嵌入式系統上，輔助圖形處理器做工程、科學、圖形運算處理，而以上複雜的運算所消耗的電能更甚於一般運算，且嵌入式系統上電源供應的條件相當嚴苛，若Shader Core消耗系統過多的電源，將使整個系統的使用壽命大幅縮短。 在此篇論文我們提出一低耗能編譯器最佳化方法，使用指令排程，將存取I/O Buffer的指令重排，使I/O Buffer的連續閒置時間延長，並搭配時脈匣控（Clock-Gating）或電源匣控（Power-Gating）在盡量]不影響效能及計算結果的前提下，將閒置的I/O Buffer關閉或降低其電壓與時脈以降低系統整體的功率消耗。我們將研究成果實作在一私有之 ESSL 編譯器，與未實作最佳化方法之編譯器比較，我們在Input Buffer平均省下53.6%的耗能，而與傳統的時脈匣控與電源匣控相比，我們將平均效能損失由7.95%降低至2.77%。

Recently graphics processing units have been widely adopted in system-on-a-chip designs and tend to be used in embedded systems for manipulating computer graphics or even general purpose computation. Energy management must be a matter of concern to either hardware or software designers. In this paper we present an energy-aware code motion framework for a compiler to generate concentrated accesses to input and output buffers inside a graphics processing unit. Our solution attempts to gather the input and output buffer accesses into clusters, thereby extending the duration of the input and output buffers being clock- or power-gated. We performed experiments by incorporating our compiler analysis and code motion framework into an in-house compiler tool and by simulating the energy consumption. The experimental results demonstrate that our mechanisms are effective in reducing the energy consumption of the input buffer by an average of 53.6% and decreasing the performance degradation from 7.95% to 2.77% compared with the naive clock-gating method.