標準CMOS製程之低暗記數單光子崩潰二極體

Abstract

本論文提出並實現了能夠降低單光子偵測器暗計數的元件結構。為避免shallow trench isolation (STI)中的缺陷在主動區誘發崩潰，我們設計保護環隔絕Shallow trench isolation (STI)，或將元件主動區由表層置換到底部，來將STI與元件主動區隔開，並利用TCAD模擬所設計結構之電場與離子化速率的空間分佈，確認設計之可行性。在本論文中我們進一步使用摻雜濃度較低的高壓標準製程，降低能帶間穿隧機率來減少暗計數。我們使用台積電0.25 □m高壓CMOS標準製程製作了設計的元件，藉由實驗室自行架設的量測系統並配合passive quenching circuit，我們進行了不同超額偏壓的暗計數量測，量測結果顯示與傳統結構相較，暗計數降低了兩個數量級以上，最低暗計數小於10 Hz，我們也透過精確校正光量的方式，量測了各元件在不同超額偏壓與入射光波長下的光偵測率，最高偵測率在波長650 nm時可達15.4%。最後，我們討論了最佳元件中暗計數的成因，並提出進一步改善的方向。

In this thesis, we propose and demonstrate a device structure of low dark-count-rate (DCR) single photon detector. To avoid the breakdown events triggered by the trap of shallow trench isolation (STI) in the active region, we design a guard-ring structure to keep the STI in distance or relocate the active region from the top region to the deeper one. TCAD simulation tool is used to calculate the spatial distributions of electric field and impact ionization to confirm the feasibility of our design. With the 0.25-µm high-voltage standard CMOS technology, we have fabricated the designed devices successfully. The DCRs of devices under various excess voltages have been characterized with the setup in our lab and with the passive quenching circuit. The results show that the DCR of designed structure is lowered by more than two orders comparing with that of the conventional one. The lowest DCR less than 10 Hz is obtained. With a precise calibration of incident power, we have also measured the photon detection efficiency (PDE) of the devices under various excess voltage and incident wavelengths. The highest PDE reaches 15.4 % at 650 nm. At last, we discuss the DCR mechanism of the best device and suggest the direction for further improvement in the future.