Title: | CMOS製程相容U型多重讀寫氮化矽快閃式記憶體之物理機制與可靠性探討 Investigation of the Mechanism and Reliability of a U-Shaped MTP SONOS Flash Memory Cell by a CMOS Logic Process |
Authors: | 蔡政達 Tsai, Cheng-Ta 莊紹勳 Chung, Steve S. 電子研究所 |
Keywords: | 記憶體;SONOS |
Issue Date: | 2012 |
Abstract: | 氮化矽記憶體 (SONOS Memory) 是近年來非揮發性記憶體的一大熱門探討主題,相較於傳統浮動閘極快閃記憶體 (Floating Gate Flash Memory),有著較簡單的結構、製程簡單,而且可以有更佳的微縮能力 (Scalability)。現今的快閃式記憶體,對低電壓操作、低功率操作、以及寫入速度等的要求愈來愈高。在本篇論文中,我們提出一種有效縮小電荷儲存節點大小之氮化矽快閃式記憶體。操作上,吾人多利用通道熱電子 (CHEI: Channel Hot Electron Injection) 的寫入機制及帶對帶電洞入射(BBHHI: Band-to-Band Tunneling Hot Hole Injection) 抹除機制來達到上述的要求。但由於離子碰撞產生的電子與電洞的交互作用可能導致穿隧化層的可靠性問題,本文將針對此元件探討一種新的電子及電洞的注入方式,來改善其可靠性。
首先,我們發展出一個順偏壓電子注入方式FBEI (Forward Bias induced Electron Injection) ,相較於傳統的操作方式,該方法為操作速度較快,且有足夠大的電壓視窗 (Operation Window) 。實驗結果比較,FBEI具有與CHEI局部儲存電荷的行為,且經由電荷密度儲存的位置中發現,FBEI的儲存位置較CHEI更為靠近汲極端 (Drain) ,此外,還具有較佳的電荷保存 (Data Retention) 特性。接著,我們提出一種基底瞬時熱電洞射入 (STHHI: Substrate Transient Hot Hole Injection) 之抹除方式可以完整的消除儲存的電子並且造成低電子電洞之差異分佈,而導致低橫向資料流失,且可以表現在10年的生命週期(lifetime)曲線上, 減低電壓區間操作視窗的縮小(window closure)。
最後,資料遺失(charge loss)是氮化矽快閃式記憶體最為重要之可靠度議題。在本論文中,我們使用有效縮小電荷儲存節點大小之氮化矽快閃式記憶體提出了導致電荷流失的機制。在不同的操作次數下,我們可以觀察到水平方向之資料遺失是由於電子和電洞間之分佈差異所導致, 且因儲存節點的縮小,一定的操作次數後資料遺失會趨於飽和。 SONOS Memory has recently received much more attention because of its simplicity in structure, process, and scalable by comparing with conventional floating gate cells. Nowadays, the requirements of flash memory, low voltage operation, low power consumption, and high speed are becoming increasingly important. In this study, a U-MTP (U-Shaped Multi-Time-Programming) SONOS flash memory with an effective shrinking of the storage node size has been proposed. By using the conventional programming scheme of channel hot electron injection and erasing scheme of band-to-band tunneling hot hole injection, the interaction of the generated electron and hole pairs could cause the reliability issue of the tunnel oxide. Then, we will be focused on a novel programming and erasing method for U-MTP SONOS applications, in which the improvement of the cell reliability will be demonstrated. First, we used an operation scheme, FBEI (Forward Bias induced Electron Injection) for the cell programming. Comparing to conventional schemes, this FBEI scheme has fast speed and large enough operation window. We found that FBEI and CHEI have a similar characteristic of the locally storage charge distribution in our experiments. Moreover, the stored charge profile of FBEI is closer to the drain than the CHEI one from the stored charge density distribution. In addition, FBEI has better data retention. Then, STHHI (Substrate Transient Hot Hole Injection) erasing scheme has been demonstrated to eliminate the electrons throughout the entire channel and achieve low electron and hole mismatchs, inducing low lateral data charge loss and being predicted a weaker window closure in the 10-year lifetime curve after the program/erase cycling in U-MTP SONOS cells. Finally, the charge loss in nitride based charge trapping memory has been considered to be a major reliability issue. In this paper, a mechanism of the charge loss in U-MTP SONOS memory has been proposed. By different cycling times, the lateral charge loss is caused by the mismatch between electron and hole distributions and with the shrinking of the storage node, in which the charge loss tends to reach saturate after a certain number of operations. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#GT079911581 http://hdl.handle.net/11536/49127 |
Appears in Collections: | Thesis |