應用於K-band之低功率吉爾伯特降頻混頻器

Abstract

本論文研究主要是在探討低功率、高增益混波器的設計，頻段則定位在K-band，設計內容包含以下幾個部分:A.輸入、輸出端阻抗匹配 B.混頻器主電路架構選定 C.RF-LO級間寄生電容的處理 D.適當選取各偏壓以正常操作 (將2nd order effect減至最低，可避免掉不必要的混頻訊號產生。) E.Layout時，訊號走線的電感與寄生電容效應 F.Buffer stage使用源極隨耦器維持整體電路線性度。 電路設計頻帶約為20.3GHz ~ 23.5GHz，on-wafer量測時中頻在200MHz在量測的結果為電壓轉換增益約4.62dB、P1dB在-8dBm、隔離度RF-_IF,LO_IF,LO_RF皆大於35dB，重點是電路設計功率消耗僅 1.43mW 在設計的過程中遇到了許多的問題，特別是在LO-stage的body effect效應使電路偏壓遭到侷限進而影響特性、0.18製程將頻率升至20GHz以上使用電感佈線的技巧…等等。 本次晶片使用台積電 0.18um CMOS 製程實現，並且在國家晶片系統設計中心進行量測，其模擬與量測結果的差異將在論文中做說明和討論。

The topic of this thesis is to research the design of the low-power mixer with high conversion gain、low noise and the bandwidth is designed at K-band(18~27 GHz). The design procedures include: (1) input and output matching networks (2) choice of the main architecture (3) The process of the parasitic capacitors between RF and LO stage (4) choice of the adjacent bias point (5) In layout, the parasitic effect of the signal’s routes (6) Source follower in buffer stage. The design procedures will explain how to overcome these problems in detail. After measurement, the circuit operates at 20.3GHz ~ 23.5GHz. And the IF is at 200MHz. The measurement results include: Conversion voltage gain is about 4.62dB, isolation (RF_IF, LO_IF, LO_RF) larger than 35, P1dB is about -8dBm. Power consumption of the circuit is only 1.43mW. There are many problems we encounter in the design process. Especially, the bias of the circuit is limited because the body effect of the LO stage、the 0.18um CMOS process at K-band, the method of layout…etc. This chip fabricated in TSMC 0.18um CMOS. The circuit is measured at CIC. There are some discussion and statement about difference between simulation and measurement in this thesis.