壓縮感測還原演算法晶片設計

Abstract

這篇論文中提出了兩個壓縮感測還原演算法改良自子空間追尋，這兩個演算法降低了源演算法的複雜度而且仍然保持著高還原率。這兩個提出的演算法和其他現有演算法的複雜度分析以及模擬結果都描述於此篇論文內，我們可以觀察到我們所提出的演算法擁有良好的效能。除此之外，此篇論文也將其中一種提出的還原演算法實做為電路，也特別設計一些硬體架構來完成此電路，我們所用的製程為台積電90奈米製程，此電路的時脈速度為100MHz，面積為11.69 mm2，而平均消耗功率為431 mW。

This paper proposes two recovery algorithms modified from subspace pursuit(SP) for compressed sensing problems. The two algorithms can reduce the complexity of SP and maintain the high recovery rate. Complexity analysis and simulation results are provided for the proposed algorithms and other conventional recovering algorithms. We observe that the proposed algorithms can perform well. Besides, this paper also proposes an architecture for one of the proposed recovering algorithm for VLSI implementation. Several hardware units are dedicated designs for the implementation. The proposed chip is implemented using a TSMC 90nm process and can use a clock rate of 100MHz with total area is 11.69 mm2. The average power is 431mW.