3.1-10.6 GHz超寬頻低功率之自我基底偏壓低雜訊放大器設計

Abstract

本篇論文的研究焦點，著重於如何降低低雜訊放大器其功率消耗及雜訊指數。一般是採用基底偏壓技術，利用電阻回授產生足夠的壓降，以提升基底端的電位，使得電晶體的過驅電壓Vt降低，即可降低供應電壓，而一般使用電阻基底偏壓，雜訊易從基底端洩漏造成較高的雜訊指數。本電路的設計架構是根據基本架構改良，我們以電晶體基底偏壓來取代傳統架構中的電阻，因電晶體的雜訊主要來至尺寸的大小，不同於電阻的是電晶體是非線性元件，所以我們只需要選擇小尺寸電晶體，即可在汲-源端產生足夠的壓降，是個有效抑制雜訊的方法。由於電晶體的寄生效應使得頻率響應的極點往低頻移動，為了改善我們在輸入級採用CG+CG疊接架構，並加入中心抽頭電感作為增益的補償，在輸入級電晶體與基底偏壓電晶體之間，由中心抽頭處控制自我偏壓的大小，也能節省額外的偏壓電路，使基底偏壓的電晶體與汲極端的電感形成Gm-boosted架構，增加其高頻響應與S12之隔離性。 其量測結果如下所述：頻寬為3.1~10.6 GHz，輸入與輸出反射損失皆大於10 dB，最大增益為14 dB，最低雜訊指數為3.2 dB，在3.1 GHz,6 GHz的P1dB增益壓縮點分別為-13 dBm和-12 dBm，IIP3截斷點分別為-2 dBm和-3 dBm，核心電路消耗功率為8.95 mW，整體佈局面積包含pad為0.84*0.89=0.75 mm2。

In this thesis, the research focuses on how to reduce the power consumption and noise figure. In general, the substrate bias produce a sufficient voltage drop using resistor feedback to enhance the potential of the substrate side, decreasing the over drive voltage (Vt) of the transistor can reduce the supply voltage . Usually, it could use resistive body bias but noise was easy leak from the base end result in higher noise figure. The design of the circuit architecture improved the basic framework , we use transistor body bias to replace the traditional architecture of the resistor body bias, because the noise figure of the amplifier come from the size of the transistor. It is different from the resistance, the transistor is a nonlinear element, so we only need to select the small size of transistors, and then generate enough voltage drop in the drain - source end. It is an effective noise suppression. Because the parasitic effect of the transistors makes the frequency response of the pole move to the low frequency band. In order to improve the problem, we adopt the CG the CG cascode architecture in the input stage and join the center-tapped inductor as gain compensation. The center tap inductor can control the voltage of the self body bias, and it can also save an additional bias circuit, so that the substrate bias transistor and the drain inductance form the Gm-boosted architecture to increase its high-frequency response and the S12 isolation. The measured results are as follows: bandwidth of 3.1 ~ 10.6 GHz, input and output reflection loss are greater than -10 dB, the maximum power gain is 14 dB, the minimum noise figure is 3.2 dB, at 3.1 GHz and 6 GHz, the P1dB gain compression point is -13 dBm and -12 dBm, the IIP3 cut-off point is -2 dBm and -3 dBm, the core circuit power consumption is 8.95 mW, and the overall layout area including the pads is 0.84 * 0.89 = 0.75 mm2.