視訊品質控制之軟硬體協同設計與純粹硬體方法

Abstract

大部分軟體為主的視訊編碼器會在動作預測之後，對頻寬及失真作分析來確定量化器的大小，由動作預測單元得到的絕對誤差總和被使用來估計頻寬控制模式中的編碼複雜度。對於SoC平台上的視訊編碼器來說，如果要達到較佳的頻寬控制效能，由於需要計算複雜的數學模式，比較適合由微處理器來計算，而區塊編碼迴圈則是由VLSI加速器來執行。為了降低微處理器與加速電路溝通上的負荷，因此本論文設計出一套能在編碼迴圈外獨立執行的頻寬控制模式的方法。這個方法除了控制視訊編碼的資料流量之外，並可作場景變換偵測。另外，為了更進一步降低溝通上的負擔及簡化系統匯流排的設計，在此亦提出了查表方式的頻寬控制模式，用查表的方式取代複雜的碼率失真數學模型的計算，此演算法十分適合直接做在加速電路之中。總結而言，在此論文中，我們提出了一套適用於SoC平台上的視訊編碼器的迴圈外頻寬控制演算法，以及一個查表方式的頻寬控制演算法。由實驗結果可知，這些方法的效果極佳，很適合用在實際的系統中。

Most software-based video encoders perform rate-distortion model analysis to determine the quantizer step size after motion estimation (ME). Typically, Sum of Absolute Differences (SAD) from the motion estimator is used as the complexity estimates for rate-control model. However, for video encoders on SoC platforms, the calculation of rate-control model is typically done on the microcontroller (MCU) core while the macroblock encoding loop (ME, transform, quantization, and entropy coding) is executed by ASIC accelerators. In order to reduce the communication overhead between the MCU and the ASIC accelerator, this thesis proposes a rate control algorithm that can be executed outside the encoding loop solely by the MCU is very useful. In addition, this thesis also proposes a lookup table approach that is suitable for pure hardware implementation. In this approach, the sophisticated R-D model is replaced with a lookup table and low complexity VLSI architecture can be used for rate-control for ASIC accelerators. Experimental results show that these algorithms are very promising for video codec hardware/software co-design and pure hardware implementation in practical systems.