應用於後矽驗證中錯誤偵測及重現之嵌入式除錯架構

Abstract

隨著數位裝置的普及, 晶片系統的應用越來越廣泛, 後矽驗證已經成為不可或缺的一部分。 在晶片設計中, 確保所設計的晶片能正確運作是一個重要的階段, 然而, 隨著晶片功能提升, 設計複雜度相對提高, 晶片系統整合的驗證困難度逐漸上升, 因此, 後矽驗證佔據了整體現代晶片設計上的絕大多數時間。 本論文提出一嵌入式除錯架構以偵測與重現於後矽驗證中常見的錯誤。 在此除錯架構下, 系統層級的錯誤能於晶片測試中即時地被偵測, 使得導致此錯誤的真正原因能快速地找出。 另外, 透過本論文提出的時間標記機制, 系統具有重現錯誤之能力, 而時間標記在經由後製處理後, 其所佔用空間與錯誤重現時的系統負擔被大幅地降低。 實驗結果顯示, 此除錯架構能改善大於80%的除錯時間, 49%~56%的儲存空間, 以及大約46%的重現錯誤時的系統負擔。

As digital devices and system on chip (SoC) are becoming prevalent in recent years, post-silicon validation has been indispensable for SoC designs. In SoC designs, it is crucial to test the design correctness for product success. However, the complexity of modern SoC designs keep increasing, it is difficult to cover all behaviors in manufactured chip by existing validation techniques. Therefore, post-silicon validation is a major challenge for future systems. This work proposes an embedded debugging architecture for bug detection and reproduction during post-silicon validation. In the debugging system, system-level bugs are detected in real-time for accurately localizing bugs. In addition, by using the timestamp mechanism provided by the debugging system, the tested system is capable of reproducing bugs for cyclic debugging. Further, the storage and bug reproduction overhead are significantly reduced by using special post-analysis techniques. The experimental results show that the debugging system improves (1) debugging execution time > 80%, (2) storage overhead 49% ~ 56% and bug reproducing overhead ~46%.