微影製程切割道縮減之研究

Abstract

半導體製程技術在降低成本之技術發展的兩大趨勢即是製程技術上的微縮以及晶圓尺寸的增大。以黃光微影製程角度而言，其晶粒面積的組成也包含著晶粒之間的切割道，其主要用途除了作為晶粒切割所需的空間外，另放置重合誤差量測標誌(Overlay Mark)及曝光機台所使用的對準標誌(Alignment Mark)，也供放置電性測試鍵(WAT Test-key)讓晶圓在出貨前測試電容電阻等值。本論文研究之主要目的為藉由晶圓上之切割道縮減後，在相同IC製程下，晶粒組成的面積變小，可以增加最後總產出晶粒並達到降低生產成本之效果。 (1)經由變更縮減切割道所需之設計後，訂製新光罩，以曝光顯影後確認之Alignment訊號波形比對於正常切割道Alignment訊號波形強度，由量測數據趨勢圖進行分析，以驗證切割道縮減後之對準訊號差異。 (2)量測切割道縮減後之重合疊對誤差及X & Y方向±3σ值之穩定度，比對正常切割道的數據後進行分析，以驗證切割道縮減後之重合疊對誤差差異。 (3)在完成全製程及電性測試數據確認符合規格後，即出廠測試良率，由電性測試數據及客戶回傳良率數據比對於正常切割道之數據，以管制圖及變異數分析檢定驗證縮減後之可行性。 關鍵字：切割道縮減、Alignment訊號波形、重合誤差量測

Semiconductor process technology needs continuous efforts to lower the cost of yielded chips. Two major developments on the process technology to achieve this goal are larger wafer size and line width reduction. In terms of photolithography process, the composition of the chip area also contains scribe lines, and its main usage is to place the “Overlay Mark” and “Alignment mark” which are necessary in exposure machine, and to separate chips in dicing process. In addition, it also put electrical test-key (WAT test-key) to test capacitance, resistance for wafer shipments. By the process of reducing the width of scribe lines, it is possible to increase the yield per wafer in the same IC process. The main purpose of this thesis is to study the effect of reducing the scribe line width to the photolithography process. The methodology of research is as following steps: (1)Via the reduction of dicing line width design and custom-made new mask, confirm alignment signal’s waveform after exposure and developing process. Compare normal scribe line width results with experimental samples. Then verify the difference of measurement data by trend chart. (2)Measure the stability of coincide overlay error data (±3σ) for X & Y direction. Compare the data with normal scribe line width results, and do analysis to verify the difference between normal and scale-down scribe line. ii (3)Complete the whole wafer process and meet the specifications of electrical data, and then test the yield by customers. Base on the electrical and yield data reports, we can confirm by control chart and variance test analysis to verify the feasibility of scribe line width reduction. Key words︰Scribe line width reduction、Alignment signal wave form、Overlay error