高速互補式金氧半元件之設計考慮

Abstract

本文研究通道離子佈植濃度對通道內載子分佈之關係，並將這種關係引進通道內載子遷移率的理論模式內，可以得到一個較完整和準確的載子遷移率計算模式。同時也研究離子佈植濃度對載子遷移率的最佳化分佈，藉此而得到較高的載子遷移率。實驗結果顯示修正後的載子遷移率模式，與測量的數值誤差在百分之三以內。 此外，本文也提出一種新的尺度縮小法則，並且利用修正後的載子遷移率模式評估元件尺度縮小後，傳統的縮小法則—等電場，等電壓及準等電壓三種與新的尺度縮小法則在載子遷移率與飽合電流的差異。最後並以持續合成與分析(TISA)之電路分析程式証實新的尺度縮小法則具有較快的速度表現，可以滿足高速互補式金氧半元件的設計要求。

In this thesis, the variation of the carrier distribution in the inversion layer by quantum mechanics for B+ and BF2+ channel implantation is researched in detail. The carrier mobility which considers the above-mentioned variation and normal field mobility degradation is more complete and accurate than the conventional one in MINIMOS. The simulation results of the mobility model show that there is about 10% error in the measurements. The modified mobility model which fitted by the experiments can reduce the error to below 3%. From the comparison of the mobility between B+ and BF2+ channel implantation, an optimal channel implantation to get the higher mobility is obtained. The basic scaling laws contain constant field, constant voltage and quasi-constant voltage, which have a lower mobility degradation and lower saturation current. From the point of view of speed, a new scaling law which has a lighter scaled voltage and a greater scaled gate oxide thickness than the basic scaling laws is proposed. The comparisons between the basic scaling laws and the new one in saturation current, mobility, and circuit speed of TISA (Timing Synthesis and analysis) are used to find an optimal scaling law. The results of simulation reveal that new scaling law which with a larger mobility degradation and higher saturation current gets the better circuit speed, and a maximum increase ratio in circuit speed. Therefore, the new scaling is obtained which can be used in designing of high-speed CMOS.