非飽和雙極性邏輯電路的新型延遲模式化技術和物理時序與其在電路性能改進之應用

Abstract

本論文首先提出一以電流為輸入╱輸出信號的非飽和性雙戴子電晶體之新型大信號等 效電。根據此等效電路發展出DCTL 和適用於小並聯電容Ce的NTL 之物理時序模式方 法。並經由SPICE 模擬結果此較及NTL 環形振盪器之實驗印證，其誤差均在25%以下 。 進而用此雙載子電流域等效電路暨電流域分析技術發展一套適用於Ce值較大範圍的雙 載子NTL 物理時序模式，使其可適用於高速率且低功率的NTL 設計。在不同的元件及 電路參數下，由此模式計算轉換時間之誤差在10％%以，內而延遲時間計算結果之誤 差在16％以內。同時此時序模式亦用來發展一套雙載子NTL 電路的尺寸和Ce設計方法 。由此研究中發現NTL 電路存在一Ce的臨界值Ceo (此時NTL 電路不發生電流或電壓 之超越或欠過情況)，而Ce 之最佳化設計在1∼1.25Ceo之間。同時本論文亦提出Ceo 的完整的和簡化計算模式。這些模式和設計方法都進一步的應用於NTL 閘的尺寸設計 、緩衝器的設計例子中。 相同之理念亦成功的應用於開發雙子CML 電路之新型物理時序模式。經由廣泛SPICE 模擬結果之此較，印證此新型CML 時序模式有良好準確性。其中CML 反相器的轉換時 間之計算誤差在10％以內而延遲時間之計算誤差在15％以內，CML 多輸入NOR╱OR 閘 的設計規範。其中發現固然增加等效射極電容Ce可有效的減少延遲時間，但由於Re大 於某值時其將會有電流超溢發生，而此現象將限制可用的Ce值範圍和CML NOR 閘輸入 數目。 由於所提出之電流域等效電路及分析技術既簡單又可促使複雜的高速雙載子邏輯電路 延遲時間模式變成有效率和可分離且可分析的模式，這些方法將可適用於其他的高速 隻載子邏輯電路系列。相對於數值模擬方法，這些電流域物理模式擁有消耗少量CPU 時間及記憶體量且有良好的精確性和寬廣的元件暨電路參數適用範圍等點。這些優點 令這些電流域物理時序模式適用於高速雙載子之超大型積體電路的電腦輔助設計和最 佳化設計。 /////// results that the models have a maximum error of 25% in single-stage delay calculation and 10% in multi-stage delay calculation. Experimental results on NTL ring oscillators also partly substantiate the developed current-domain large-signal equivalent circuit and physical timing models. Physical timing models have also been derived by using the current-domain BJT equivalent circuit and the current-domain analysis technique for high-speed low-power bipolar NTL circuits with a wide range of Ce. It is shown that the errors of model calculation are below 10% for transition times and 16% for delay times of NTL gates with different device and circuit parameters. The design methodology of Ce and the emitter length of bipolar NTL circuits have also been developed from the timing model. It is shown that the optimal value of Ce is equal to 1~1.25 Ceo where Ceo is the shunt capacitance of NTL circuit without voltage or current overshooting and undershooting. Both exact model and simplified model for Ceo has been derived. Applying the developed timing models and design methodology, the sizing of NTL gates and taper buffers have been successfully performed as application examples. New physical timing models based upon the current-domain large-signal equivalent circuits and the new modeling technique have been successfully developed for bipolar CML logic circuits. The model calculation results have been extensively compared with SPICE simulation results and the good accuracy of model calculations as well as the correctness of the equivalent circuit and the model ahve been verified. For CML inverters, the model errors are below 10% for transition times and 15% for delay times. For CML multi-input NOR gates or OR gates, the errors are below 10%. Based upon the developed physical timing models, the design guidelines, requirement and limitation of CML multi-input CML NOR or OR gates have also developed. It is found that the gate delay time is decreased with increasing the effective emitter capacitance Ce. But current oveshooting occurs as Ce or the effective emitter resistance Re is greater than certain values. This puts a limit or requirement on the Ce value, the BJT device design, and the fan-in number of the CML gates. Since the proposed current-domain equivalent circuit and analysis technique are simple and makes the delay modeling of complex high-speed bipolar logic circuits analytical, separable, and efficient, their application in modeling other high-speed bipolar logic families are feasible. Moreover, good accuracy, wide applicable ranges of device╱ circuit parameters and input waveforms, and less CPU time and memory consumption than full transient simulations make the developed currect-domain physical timing models of bipolar nonsaturation logic full of potential in applications of optimization and CAD of high-speed bipolar VLSI.