多處理機系統中輸入/輸出橋接器之設計與製作

Abstract

為了降低緊耦合多處理機系統中共用匯流排的負載，常會在ＣＰＵ與共用 匯流排之間，插放一個後寫回式的快捷記憶體以降低ＣＰＵ對共用匯流排 負載之影響。然而，輸入/輸出系統對於共用匯流排負載之影響卻較少被 考慮到。輸入/輸出橋接器是指介乎共用匯流排與輸入/輸出系統間的一個 橋接器。它的架構會影響輸入/輸出系統加諸於共用匯流排的負載。在本 論文中，我們首先概觀輸入/輸出橋接器的可能架構。其次，我們設計一 個能有效降低共用匯流排負載的輸入/輸出橋接器。在此設計中 ，將包含 一個快捷緩衝器，同時，我們也發展一個硬體的匯流排監視協定 (Snooping Protocol)以解決資料一致性問題。最後，我們針對所設計的 輸入/輸出橋接器和其它輸入/輸出橋接器作效能評估以比較它們對共用匯 流排負載之影響。 To reduce the load of the share bus in a tightly-coupled multiprocessor system,write-back cache is often inserted between each CPU and the share bus.However,the impact on the share bus load from I/O side is seldom considered. I/O bridge is referred to a bus bridge between the share bus and the I/O bus.Its organization is believed to affect the share bus load imposed by I/O activity.In this thesis,we first survey possibile I/O bridge organizations.Then,we design an I/O bridge architecture which can effectively reduce the share bus load imposed by I/O.In this design, a cache buffer is added to the bridge and a H/W bus snooping protocol is developed to solve the data coherence problem.Finally, performance evaluation is conducted to compare the share bus load impacts of the proposed bridge design and other possible bridge designs.