標題: 一個提供超純量多處理機系統設計之模擬及路徑環境
A Simulation and Trace Environment for Superscalar based Multiprocessor Design
作者: 陳財木
Wood Chen
陳 正
Cheng Chen
資訊科學與工程研究所
關鍵字: 多處理機, 超純量, 模擬, 分享記憶體, 平行, 簡化指令集;Multiprocessor, Superscalar, Simulation, Shared-memory, RISC, Parallel
公開日期: 1992
摘要: 本論文之目的在對超純量為基礎的分享記憶體 (Share Memory) 多處理機 系統設計上的重要考慮作探討,並設計一個模擬系統 (Superscalar based Multiprocessor Simulation and Tracing System ,簡稱 SMSTS) 作為研究設計上的重要環境。SMSTS是一個軟體模擬系統,用來 模擬一個以超純量為基礎的多處理機 (Multi-Processor 簡稱 M.P.) 系統架構;其目的為模擬 M.P. 系統中所有處理單元 (Processor Element,簡稱 PE) 的平行執行環境,以得到 M.P. 系統執行時正確 的路徑,而此路徑所對應的記憶體存取行為 (Memory Access Behavior) 則經由記憶體模擬器 (Memory Simulator) 的模擬,以獲得此 M.P.系 統整體的評估資訊做為設計者主要的依據考量。本模擬系統利用一平行化 的時序控制模式 (Timing Control Model) ,而可建立在單一工作站上 ,或將來分散於多台工作站上作平行模擬。且彈性地提供O.S.、M.P.架構 、記憶體模擬器及 PE 模式之探討,針對不同的需求作模擬,並且提供非 指令插入式的 Monitor 及 Debuging 環境;使設計者能效率、彈性地 模擬,以達到有效的評估、改善之設計目標。目前,我們已將此模擬環境 建立於 SUN、 IBM 工做站上,以 C 語言設計完成;此外,並針對我們的 超純量M.P.系統做驗証評估工作,包括 M.P.系統中通訊花費( Communication overhead)、超純量指令層次平行化、記憶體延遲( Latency)、延遲隱藏、...等特性之探討;並依據超純量在 M.P.系統設計 上的特性,提出設計重要之考量準則。 In this thesis, we disscus the issues of superscalar based shared-memory multiprocessor design. And we have developed a simulation system named SMSTS (Supersacalar based Multiprocessor Simulation and Tracing System) as an useful environment for exploring some important design issues. SMSTS is a software Simulation based on superscalar PE (Processor Element) for shared-memory multiprocessor system. It's used to obtain data and generate parallel program's traces for evaluating the multiprocessor system and behavior of superscalar PE. The supersclar PE is retargetable by the description of machine SPEC, and can link with variable architecture simulator for each M.P. environment. Our simulator is designed by a parallel timing control model, that can be built in a workstation or easily port to multi-workstations in the future. It provides a flexible simulation environment for the discuss on different O.S. , M.P. memory architecture, and PE models.SMTS also provides system designer a non-instructive debugging and monitoring environment. We have already used it to evaluate our designed superscalar M.P. system, including the issues of communication overhead, superscalar instruction parallelism, memory latency, latency hidden ... and so on, then propose some design criterions for the superscalar M.P. system.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT810392031
http://hdl.handle.net/11536/56760
顯示於類別:畢業論文