完全搜尋區塊比對演算法之 VLSI 陣列設計

Abstract

本論文中, 我們提出完全搜尋區塊比對演算法 (Full-Search Block Matching Algorithm) 之 VLSI 陣列. 完全搜尋區塊比對演算法之 VLSI 陣列可用來尋找影像序列移動物體參數, 以達到影像序列的壓縮. 我們分 析完全區塊比對演算法, 發現完全區塊比對演算法可用兩種公式來表示. 應用系統化的方法我們可由這兩種型式設計出 48 種 VLSI 陣列. 為了分 析各陣列的效能我們提出一些評估參數, 並提出刪除步驟刪掉效能較差的 陣列. 將效能較佳的陣列放入陣列評估表中. 在陣列評估表中我們列出各 陣列的速度, 硬體成本, 輸出入要求等參數, 以供實際應用能迅速找出 符合需求的 VLSI 陣列. 為了提高陣列的效能, 我們用雙層管線 ( two- level pipelined)來重新設計陣列. 雙層管線設計中我們將管線階層降至 算術單元, 縮短了管線階層的時間, 提高了陣列的輸出率, 增加了陣列的 效能. 因此應用系統化的方法我們重新設計出 48 種雙層管線 VLSI 陣 列, 對不同應用的需求我們使用評估參數, 刪除步驟及陣列評估表來尋找 符合條件的雙層管線陣列. 我們所設計出來新的 VLSI 陣列及雙層管線 VLSI 陣列,用陣列評估表跟其他文獻所設計出來的 VLSI 陣列做比較, 發 現我們所設計出的陣列比文獻中的陣陣列有較少的硬體成本及增加執行的 速度. In this thesis we discuss the design of VLSI arrays for full -search block matching algorithm. The full-search block matching algorithm has been widely used for finding the motion parameters in image sequence to attain high image compression. Analysis the full-search block matching, we find it can be represented by two formula. We analyze the two formulations and find that forty-eight VLSI arrays can be results. We present some performance criteria to evaluate these arrays and give a strategies to delete those arrays which does not have satisfying performance. Through this step, we can obtain some candidate arrays. We summarize these in a table with request to performance criteria. Through the table, user can find the requirement. To further increase the computing speed,two-level pipelining has been adopted to redesign arrays. Based on a similar design procedure as that for VLSI arrays, we give the candidate arrays and summarize these arrays with a table. This paper show that the design arrays have a lower hardware cost and higher computing speed than existing arrays.