高速率數位用戶迴路傳輸中岔路器之最佳化設計

Abstract

在高速率數位用戶迴路中, 可利用銅線來完成低成本而高達每秒鐘 1.544 Mbits 之 T1 傳輸服務, 此架構是採用兩對線各傳每秒800 Kbits 之雙向傳輸方式來達成, 為了避免在雙向傳輸中所造成的回音, 必須採取 較佳之回音消除技術, 若能在岔路器設計中, 適當設計平衡電路, 回音即 可降低, 如此一來, 可使類比數位轉換器與回音消除器的設計變得較為簡 單.在本論文中, 考慮在岔路器中的平衡電路連接上, 採用平行與串接兩 種架構, 並嘗試幾種由電阻電容及電感組成之簡單平衡電路作最佳化設 計, 透過 Simplex Algorithm 調整各元件, 使得殘餘回音達到最小 . 同時, 經由比重函數的適當使用, 可降低回音脈衝效應之尾部來節省回音 消除器中所需的節點數. 此外, 串接架構之岔路器亦可用以縮短傳輸脈衝 效應之尾部, 以簡化回授等化器之設計.針對各種不同迴路所得到之最佳 化元件值, 可取其平均作為設計之依據, 以達到折衷的性能. 使用電容交 換式濾波器或動態電阻電容濾波器的方式均可達到無電感的線路設計, 並 可以應用在超大型積體電路中. Economical delivery of T1-rate data (1.544Mbits/s) over the copper loops can be realized with the high speed digital subscriber line (HDSL). An architecture, referred to as " dual duplex", on each wire-pair , uses two loops for carrying full duplex data at 800 Kbits/s each . To combat the echo problem resulted from full duplex transmission,a good echo cancellation technique should be applied . With a properly designed balance network in the hybrid circuit,echo can be reduced.The reduction in the dynamic range between near-end echo and far-end signal amplitudes makes the design of A/D converter and the subsequent task of echo canceller easier. In this thesis, we consider two structures (parallel and series) for the connection of the balance network in a hybrid circuit for front-end echo cancellation . Several kinds of balance network composed of R, L,C components are used for the optimization among different loop compositions . The simplex algorithm is applied to minimize the residual echo after the balance network . Unbalanced echo impulse responses generally have long and slowly decaying tails.We can specify a weighting function in the procedure of optimization to minimize the tail part of echo response to reduce the required number of taps in the echo canceller.The series structure hybrid circuit can also be designed to shorten the tail of the transmission (channel) response and ease the design of a decision feedback equalizer. The above optimization of the balance network is performed for each loop individually . In actual implementation of the hybrid circuits , we can average the optimal design for a compromise performance. Switched-capacitor filters and active- RC circuits can be used in inductorless implementation of the balance network. And they can be implemented in VLSI.