次微米大斜角植入式金氧半元件之特性分析與設計準則

Abstract

近年來,諸多汲極結構已被廣泛地用於次微米 MOS 元件中, 以改善熱電 子效應．具有部份重疊閘汲結構之傳統 LDD(Lightly doped drain) MOS 元件, 本質上即有側壁導致退化的效應, 為因應此一問題, 新的閘汲 重疊結構, 諸如 LATID(LArge-Tilt-angle Implanted Drain) 元件可用 以達成此一目的. 因此, 本研究將著眼於此新開發之 LATID 元件的最佳 化設計, 以及元件性能和對熱載子效應可靠度之評估.本論文中, 吾人首 先發展一套結合製程, 元件以及電路模擬之整合環境, 其中製程模擬器 (SUPREM IV) 及元件模擬器 (PISCES-2B) 乃經由目前 0.7um LATID MOS 元件製程加以調整和校正, 藉由參數之修正, 諸如二維雜質分怖, 移動率 模式以及游離衝撞係數, 吾人可獲得與實驗值甚為吻合之模擬汲極和基片 電流. 進而完成具有效通道長度為 0.3um 之 0.6 um n-通道 LATID 元件 的最佳化設計. 論文中,我們採用實驗設計法即所謂的 "反應面方法" 做 元件的最佳化設計之用. 此外, 本論文亦提供了 LATID 元件之一般化設 計準則.對 LATID 元件而言, 其具有較大的電流驅動能力和較快的電路切 換速率等優點, 但它卻具有較嚴重之短通道效應, 因而降低了它的臨限電 壓值. 另外,該元件有較大的汲源串聯電阻. 而此兩種特性和因大斜角植 入所造成的低汲-源崩潰電壓效應將會對未來深次微米極大型 (ULSI) 元 件造成設計及應用上極大的限制. In recent years, various drain structures have been widely ed to alleviate the hot electron effect in submicron MOS devices. Conventional LDD MOS device which has a partial- overlap drain structure, has an inherent spacer - induced degradation. New overlapped structure devices such as the LATID (LArge-Tilt- angle Implanted Drain) devices have been developed as such a need to avoid the spacer-induced degradation and to improve the device performance. Here, studies will be focused on optimization of a In this thesis, first a simulation environment using process, device and circuit simulation in coupled form is developed. The process (SUPREM IV) and device (PISCES-2B) simulators have been modified and calibrated against the current 0.7um LATID MOS devices by adjusting physical parameters such as those in 2-D doping profile, mobility model and the impact ionization so that experimental verification of the simulated drain and substrate current can be justified. Then, the optimum design for a 0.6um n-channel LATID device with effective gate length 0.3um can be achieved. Here, an experimental design method which is the so called Response Surface Method (RSM) is used for a scaled device design. At the same time, the design guidelines for the LATID device are also provided in this thesis. LATID MOS device has larger current drivability and higher circuit switching speed. But LATID suffers more short channel effect induced threshold voltage lowering and has higher source -and-drain series resistance. These two properties and the lower punchthrough voltage which may put a limit on its application to the future deep-submicron ULSI design.