降低互補式金氧半電晶體電路之功率消耗的研究

Abstract

當超大型積體電路的複雜程度越來越高和速度越來越快，功率消耗常會限 制現代電子系統的進一步發展。在本篇論文中，我們提出一種名為輸入重 排的方法來改進互補式金氧半電晶體電路的表現。此種方法可以在不增加 佈局面積和不需降低速度的情況下，節省邏輯閘可觀的功率消耗。輸入重 排是藉重新排列輸入的方式以減少邏輯閘的傳播延遲，轉換時間和功率消 耗，並不會改變邏輯閘的功能。因為金氧半電晶體並非理想的元件，在邏 輯閘的輸出改變狀態前，就已經有電流產生。因此如果我們正確的將邏輯 閘的輸入訊號排列，就可以增加邏輯閘的速度並減少它的功率消耗。輸入 重排的最大好處是它相容於其它的省電理論，並且不受電路的種類和技術 影響。 As the speed and complexity of VLSIs continue to improve, power dissipation is limiting the advance of modern electronic systems. A method which uses input reordering for the performance enhancement of CMOS circuits is presented. The proposed technique achieves significant reduction in power dissipation of logic gates without extra layout area or decrease in speed. Input reordering does not change the functionality, it reorders the positions of inputs to reduce the propagation delay, switching interval and power dissipation. Since MOS transistors are not ideal devices, current will occur before the output nodes of logic gates begin to change states. Hence if we properly order the input signals of a gate, the gate will speed up and consume less power dissipation. The most important advantage of input reordering is that it is orthogonal to other low power algorithm, and invariant to the type and technology of circuits.