可程式化之Viterbi解碼器架構設計

Abstract

用於通訊傳輸的迴旋碼(convolution code)其最常用的解碼方式就是 Viterbi演算法，因此在很多通訊應用上都用得到Viterbi解碼器 (VD) 。 在本論文中，我們提出一可程式化之VD。 @ 當解碼器之受限長度愈長 時，錯誤更正的效果愈好，然而其複雜度將是指數函數地增加。經由程式 摸擬，我們定出可程式化VD之設計規格，使其具有解迴旋碼(2,1,m), m=2,3,4,5 之功能。此可程式化VD為循序處理之架構，很簡單地可實現最 佳解碼(best state decoding) 之解碼方式，如此節省了很大硬體面積且 生存路徑 (survivor path) 之架構為暫存器交換(register-exchange) 之方式，其使控制電路非常簡單。由1.2 micro meter CMOS之技術，操作 頻率可達 35MHz，而晶片大小為4.9mmx6.8mm 。 The Viterbi algorithm (VA) used in decoding convolutional code is widely used in modern communications. For the widely use of Viterbi decoder, we proposed a programmable Viterbi decoder (VD) in this thesis. The performance of VD is better when the constraint length K ( K = m+1 , m is register length ) is larger. However, the complexity increase exponentially with K. Via software simulation , we specify the design parameters for the programmable VD to decode the ( 2, 1, m ) convolutional codes with m = 2, 3, 4, and 5 and choose the truncation length to be 20. The VD can be programmed by given any generator polynomials with constraint length less than 6. The architecture is the node-serial. The best state decoding (BSD) method can be easily constructed with node-serial structure to save a lot of chip area for path memory. The survivor path memory is constructed by register-exchange method with only simple control circuit needed. By 1.2 micro meter CMOS technology, the operating clock rate can be up to 35 MHz and the final chip size is 4.9 mm x 6.8 mm.