視訊編碼器中移動補償之設計與硬體實現

Abstract

在Ｈ．２６１、ＭＰＥＧ，甚至在ＨＤＴＶ中，區塊對照演繹法是廣泛地 拿來當作動態預估的標準。在這麼多關於區塊對照演繹法的方法中，全尋 比對是計算量最大的一種。這種方法的優點是擁有較小的預估誤差，規則 的資料存取、資料流動和計算順序。這個架構用 Verilog 來做行為模式 (behavior level) 的模 擬，用IRSIM做電路佈局(layout) 的驗證。用 tsmc0.8mm 技術，可以得到大小為4.8mm X 5.6mm，電晶體數目為 94555的晶片。跟據SPICE模擬的結果，臨界路徑(critical path)的延遲 時間 (delay time) 可達 12.5ns。 Block matching algorithm (BMA) is a widely adopted motion estimation criterion in many standard proposals such as H.261, MPEG, and possibly HDTV. Among the many approaches according to BMA, full search (exhaustive search) is the most computation- intensive one. The advantage is its lower estimation error and regular data access, data flow,and computation sequences. In this thesis we design an architecture for Full Search Block Matching (FSBM) which is cascadable for different speed requirements and expandable for different size of search area. The behavior of this architecture has been simulated using Verilog, and its layout is verified using IRSIM. With tsmc0.8um technology,the die size is 4.8mm$*$5.6mm and the total transistor count is 94555. According to the simulation results of SPICE, the delay time of the critical path is 12.4ns at T=100 oC.