高速數位用戶迴路等化器之設計及製作

Abstract

高速率數位用戶迴路使用等化器去除嚴重的干擾及雜訊,在不同等化方法 的傳接器中,以Nyquist取樣速率的分數間距等化器(FSE)及判定回授等化 器(DFE)之架構較佳．在此論文中將使用符號最小均方差演算法(signed LMS algorithm )及最小均方差演算法(delayed LMS algorithm),以簡化 分數間距等化器及判定回授等化器(Fractionally-spaced equalizer/ decision -feedback equalizer)(FSE/DFE)之硬體架構,並與最小均方差 演算法 (LMS algorithm)作模擬比較．為了加快FSE/DFE 的運算速度,將 提出兩種有限脈衝響應濾波器(FIR filter)作分析．在硬體設計上有限精 確度(finite-precision)之決定相當重要,因此對不同位元數作了一些效 益評比,此外也作了一些Verilog模擬分析,並也對電路實現做了一些探討 與設計． To mitigate the signal corruption due to channel-induced distortion and noise, an high-speed digital subscriber line (HDSL) transceiver has to use an equalizer. Among the different equalization methods, a decision-feedback equalizer equipped with a fractionally-spaced feedforward filter (FSE/DFE) has been shown to yield superior performance compared to a baudrate -sampling equalizer. To simplify the hardware, we consider signed LMS and delayed LMS algorithm, and we compare their performance with the usual LMS algorithm. To further reduce the computational complexity, we explore two recently proposed finite-impulse response (FIR) filter structure for implementation of the equalizer and analyze their performance. The effect of finite-precision arithmetic is analyzed by way of computer simulation using different wordlengths in computation. Verilog simulation is carried out to verify our final design at a relatively low level. We also discuss the actual circuit design for the FSE/DFE.