完整後設資料紀錄
DC 欄位語言
dc.contributor.author黃添壽en_US
dc.contributor.authorTang-Show Hwangen_US
dc.contributor.author鍾崇斌en_US
dc.contributor.authorChung-Ping Chungen_US
dc.date.accessioned2014-12-12T02:11:54Z-
dc.date.available2014-12-12T02:11:54Z-
dc.date.issued1993en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT820392042en_US
dc.identifier.urihttp://hdl.handle.net/11536/57848-
dc.description.abstract在本論文中,我們提出了一個適用於大型共享記憶體多處理機系統的軟體 一致性方法,稱為延遲無效法 (The delayed invalidation scheme).它 是利用編譯器技術,對每個存取做不同的標示,並且動態平行及選擇性的 將過時的資料視為無效.它克服了前面方法的無效率及不足.並且它只需 要少數的額外硬體及管理快取記憶體之指令.在文中,我們證明了延遲無 效法的正確性及定性和定量的與平行明確無效法的效能做比較.而且模擬 之結果顯示延遲無效法優於平行明確無效法. In this thesis, we propose a software-based cache coherence sheme, named delayed invalidation scheme. The delayedscheme is based on a compiler time marking ofa hardware-based local explicit invalidation ofarallelism and selectivity. The delayedheme allows invalidation of partial elements inercomes some of the inefficiencies andprevious schemes. With a small amount ofware and a small set of cache managementhe proposed scheme provides more cacheabilitychemes. A correctness proof and a qualitativeluation of the proposed scheme are also providhe simulated hit ratios of the proposed scheme and xplicit invalidation scheme is given. Simulation that the proposed scheme outperforms the parallel elidation scheme.zh_TW
dc.language.isoen_USen_US
dc.subject快取記憶體;軟體一致性規約;多處理機系統;共享記憶體zh_TW
dc.subjectCache;Software Coherence Protocol;Multiprocessor System; Shared Memoryen_US
dc.title延遲無效法 -- 一個快取記憶體資料一致性軟體之方法zh_TW
dc.titleDelayed Invalidation -- A Software-Based Cache Coherence Schemeen_US
dc.typeThesisen_US
dc.contributor.department資訊科學與工程研究所zh_TW
顯示於類別:畢業論文