類神經網路應用於交換機障礙診斷專家系統之研究

Abstract

本研究嘗試以類神經網路建構一套應用於交換機障礙診斷的專家系統,以 提供由電腦自動診斷障礙的功能。發展程序是將曾經發生的障礙範例以及 專家的經驗藉由特定的演算法則,訓練在類神經網路之中,這個程序適用於 任何機型的交換機系統。本研究基於二元調適網路(Binary Adaptive Networks)具有處理二元值資料和學習快速, 運算簡單的特性,選擇它為負 責障礙診斷的類神經網路模式。並且為了解決學習時落入區域極小值的問 題，結合了模擬退火原則和BAN區域調變的性質，提出三種學習法則的改 進方法。實驗結果對學習法則提出改進方法的有效性,獲得有力的驗証.當 網路樹的大小為20000 個節點時,使用改進的學習方法情況下,對於現有的 診斷報告資料已能獲得99%以上的辨識率,而在本系統初步發展階段,對未 經訓練的輸入,若與訓練樣本之間差異在一,二個位元,則辨識率在90% ~ 95%,若差異在五個位元以上,則辨識率在70% ~ 90%, 在訓練資料逐漸增加 之後,辨識率可預期再提高。此外對於以硬體實作BAN提出了以心律陣列處 理器(systolic array processor)設計的方式,並且進一步評估了以VLSI 實作的可行性。 This research attempts to develop a neural network expert system for the diagnosis of telecommunication switching systems. The neural networks were trained with previous faulty situations of switching systems and their human diagnostic responses by means of a suitable learning algorithm. We have developed a generalized neural networks system so that by training with a fault diagnosis examples of a particular type of switching system, then the neural networks can be used for diagnosis on this type of switching system. By using binary- value data and having rapid training speed, the Binary Adaptive Networks (BAN) model and Adaptive learning algorithm are selected for the neural network diagnosis system. In addition, some modifications of learning algorithm, based on locally- tuned property of BAN and simulated annealing principle, are proposed to alleviate the local minimum on the network learning problems. The effectiveness of the modifications is presented in the experiments. From the simulation results, while the node number of a BAN is 20000, the correct diagnosis rate of a GTD-5 switching system is above 99% by using the modified learning algorithm. Furthermore, the diagnosis rate on the one bit variation of the training data is between 90% and 95%, and when the variations of training data get up to five bits the diagnosis rate drops between 70% and 90%. As the training data are collected more and more, the diagnosis rate increases quite well. We also have proposed the hardware implementation of BAN by systolic array processor architecture and evaluated the VLSI implementation feasibility of the BAN design.