完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | 趙文泉 | en_US |
dc.contributor.author | Wen-Chuan Chao | en_US |
dc.contributor.author | 莊仁輝 | en_US |
dc.contributor.author | Dr. Jen-Hui Chuang | en_US |
dc.date.accessioned | 2014-12-12T02:12:01Z | - |
dc.date.available | 2014-12-12T02:12:01Z | - |
dc.date.issued | 1993 | en_US |
dc.identifier.uri | http://140.113.39.130/cdrfb3/record/nctu/#NT820394042 | en_US |
dc.identifier.uri | http://hdl.handle.net/11536/57941 | - |
dc.description.abstract | 多槽的環是一種相當不錯的內部連接技術, 因為它避免了匯流排所衍生出 來的缺點. 但是當系統變大時, 資料在環上繞一圈的時間會成為系統的瓶 頸. 本篇論文提出一個架構在多槽環的網狀球體系統, 它是由多個多槽環 所組成以縮短繞環的時間. 這個架構和威斯康辛多立方體系統相似.但是 多立方體系統是由格狀匯流排所組成. 當系統變大時, 爭用匯流排的情況 會變的很嚴重. 在保持快取記憶體資料一致方面, 當處理器要寫入快取記 憶體而必須通知其他取用此資料的快取記憶體, 它採用的方法是通知所有 的快取記憶體, 它會占用所有的橫向匯流排. 我們稱這種方法為窺探法. 為了克服後者的缺點, 本系統採用環對應目錄法來解決快取資料一致問 題. 這個方法擁有許多的優點. 經過效能評估, 我們證實所提出的內部連 接系統的確優於威斯康辛多立方體系統, 而且在我們的架構中環對應目錄 法亦比純窺探法來的好. The slotted rings, a point-to-point unidirectional connection for multiprocessor system, is a promising interconnection technology because it resolves most of the problems associated with the bus system. However, the cycle time of the ring becomes the bottleneck when the system grows. Torus with slotted rings, which is composed of multiple rings is proposed to reduce the cycle time if the ring as well as the resulting system. It is similar to the Wisconsin Multicube built by a grid of buses. As the Multicube system grows, the bys contention will seriously degrade the system performance. Moreover, the snooping cache coherence scheme adopted by the system makes all row buses busy during invalidation. The proposed architecture adopts ring-map directory cache coherence scheme to avoid occupying too many rings during invalidation. Through some performance evaluations, it is verified that the torus with slotted rings with ring-map directory scheme is better than the Wisconsin Multicube with pure snooping scheme and the ring- map directory scheme outperforms to the pure snooping scheme in the torus with slotted rings. | zh_TW |
dc.language.iso | en_US | en_US |
dc.subject | 多處理器架構;頻寬;匯流排;快取資料一致;使無效;環 | zh_TW |
dc.subject | multiprocessor architecture; bandwidths; buses; cache coherence; invalidation; rings | en_US |
dc.title | 一個網體架構在多槽環的快取資料一致多處理器 | zh_TW |
dc.title | Torus with Slotted Rings Architecture for a Cache-Coherent Multiprocessor | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | 資訊科學與工程研究所 | zh_TW |
顯示於類別: | 畢業論文 |