Reed-Solomon編解碼器之積體電路設計

Abstract

Reed-Solomon code 是數位通訊系統上很重要的一種誤碼更正法,它對於 多重的錯誤具有良好的偵測錯誤及更正錯誤能力, 尤其是適用於整串的多 重錯誤及位置不定的錯誤。在這篇論文中, 提出一個能夠減少管線式架構 的工作週期數的架構, 因而可以增加管線式架構的使用效率, 此架構稱為 Lookforward 架構。根據此架構, 設計了一個編碼長度及誤碼更正力皆可 依照需要而改變的RS編解碼器, 編碼最大長度為 255Byte, 誤碼更正力最 高可達 8Byte, 也就是一般所稱的(255, 239)編解碼器。這個編解碼器晶 片以 0.8毫微米 SPDM CMOS的半導體製成技術完成設計, 並已送往製成。 晶片面積為61平方厘米, 包含三十 一萬顆 電晶體, 根據模擬的結果, 晶 片工作頻率可達到 50M Hz,輸出效率為 800M Bits/sec 。 Reed-Solomon code is one of the most important error con- trolling codes in digital communications. It is especially powerful for multiple errors correction, thus suitable for random and bursty errors correction. In this thesis, we pro- posed a lookforward architecture that can reduce the number of cycles in the longer pipeline stage, thus resulting a more efficient use of the pipeline structure. We implemented a (255,239) RS codec chip using the lookforward architecture. Both the code length and error correcting capability of the codec chip are programmable. This RS codec chip consists of 310,000 transistors in an area of 61mm^2 using a 0.8 μm SPDM CMOS technology. Post-layout simulation shows that it can be operated at the clock rate of 50M Hz, and the bit rate is 800 Bits/sec.