ATM 共用緩衝器交換元件之電路設計

Abstract

由於共用緩衝器架構之交換元件能較有效地利用緩衝空間, 故其成為目前 ATM 交換元件之設計主流。在本論文中, 我們針對此架構設計一個 16x16 單晶片交換元件之模組電路。這些模組電路包括了一個256 字元 乘 512位元之緩衝記憶體、一個負責佇列管理的交換控制器及一組207 MHz 的輸出入串並列轉換器。各模組電路間不同之性能需求, 使得此 ATM 共用緩衝器交換元件之電路設計極具挑戰性。我們以靜態記憶體配以動態 之控制電路來設計此特長字元的緩衝記憶體。在佇列管理器之設計上, 我 們採用一些能改善硬體運用效能的架構, 這些包括: 可省去FIFO的新穎佇 列管理技巧--「迴用式佇列管理」; 不需增加額外硬體成本而適用於多級 串接的流量及優先序之整合控制; 可改善緩衝器運用效度之新連結列處理 方式。至於高速之串並列轉換器, 我們在考慮速度、功率消耗、時脈問題 及大的電源雜訊後, 選用了特定的架構及電路型態。我們已用0.8um 的 CMOS生產技術分別製作佇列管理器及輸入串列至並列轉換器。其面積分別 為4.33x6.29mm^2 及4.33x8.26mm^2 。使用本文所設計之模組電路, 將可 組構一內含一百一十三萬八千顆電晶體、佔用1.05 x1.05 cm^2 面積之單 晶片ATM 交換元件。 In this paper, we present the circuit design of the function blocks in a single-chip 16x16 ATM switch based on the shared buffer architecture. These function blocks include a buffer memory, a queue management, and a set of 207 MHz input and output serial-parallel converters. The buffer memory has a very wide word length and is constructed by an SRAM. In the design of queue management, several architectural improvements were made in the implementation to increase hardware effeciency: a novel recycling queue management scheme was adopted to eliminate the external FIFO. The priority control and flow control for multi-stage interconnection were integrated without extra hardware overhead. We improved the buffer memory utilization by a novel link-list manipulation. As for the high speed parallel-serial converters, we adopted particular architecture and the proper logic circuits based on the considerations of speed, power consumption, clocking scheme, and ground bounce. We fabricated the queue management and input serial-to-parallel converter on two chips with a 0.8um CMOS technology. The complete single-chip ATM switch can be constructed with these function blocks on a 1.05x1.05 cm^2 chip area comprising 1,138,000 transistors.