一個測試圖樣平行障礙平行序向邏輯電路障礙模擬硬體加速器

Abstract

在本篇論文中，我們提出一個對序向邏輯電路做障礙模擬的硬體加速器。 此加速器採用了一個新近提出的障礙模擬演算法以達到測試圖樣平行處理 的能力。另一方面，障礙平行處理的能力則是由多個處理器的技巧來達成 。我們亦提出一個加權拓樸順序電路分割法來解決電路分割的問題。我們 已用Ｃ語言以行為描述的方式完成了此加速器的原型機。實驗結果顯示， 如果處理器的設計能有每秒一千萬個閘級求值的運算能力，則本加速器將 比現存的其它系統快速。最後，我們提供一個加速預測公式，可用來瞭解 加速與處理器個數之間的關係。 In this thesis, we represents a parallel-pattern parallel- fault hardware accelerator for the zero delay fault simulation for the gate level synchronous sequential circuit. A novel parallel sequence fault simulation algorithm is used to achieve parallel-pattern fault simulation, and multiple processing elements are used to achieve the parallel-fault fault simulation. A weighted topological order circuit partition methodology is proposed to add freedom with the number of processing elements. The proposed architecture is implemented in a C program in the behavior level. Simulation results show that if the evalation throughput of the processing element can be equal to or larger than 10 millions evaluation per second, the proposed architecture would outperform the existing systems. Also, a speedup prediction formula is given.