以可內容定址記憶體設計高速 Lempel Ziv 資料壓縮器

Abstract

本篇論文提出一種嶄新的超大型積體電路架構，來實現一個以LZ77為基本 演算法的高速資料壓縮器。電路架構主要區分為三個單元，分別為 content addressable memory、match logic 及 output stage。其中， content addressable memory 產生一組 hit 信號用來辨認 buffer中的 symbol 與現在輸入 symbol 相同的所在位置。這些 hit 信號隨即成為 match logic 的輸入，來尋找 buffer 中與輸入資料對應的最長字串位置 及其長度。該二項結果即是壓縮後資料的核心，並且將在 output stage 經由適當的包裝而成為最後輸出的資料。在硬體成本及壓縮比之間做一平 衡的取捨後，我們選擇 2KB 的 buffer 大小及可調整的最大比對字串長 度做為我們這一顆雛型超大型積體電路的參數。在 0.8μm CMOS 製程技 術下模擬的結果，該晶片時脈速度最高可達 50MHz。這樣的結果意味著本 晶片的發展可以處理許多即時上的應用諸如影像編碼及高速資料儲存系統 。 In this thesis, a novel VLSI architecture is proposed for high- speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units, namely content addressable memory, match logic, and output stage. The content addressable memory generates a set of hit signals which identify those positions whose symbols in a specified buffer are the same as input symbol. These hits signals are then passed to the match logic which determines one matched string and its match length and location in the buffer to form the kernel of compressed data. These two items are then passed to the output stage for packetization before sent out. By trading off hardware complexity and compression ratio, 2KB buffer size and adjustable maximum match length are considered in our proto-type VLSI chip. Simulation results show that, based on a 0.8μm CMOS process technology, clock speed up to 50MHz can be achieved. This implies that the developing data compressor chip can handle many real-life applications such as in video coding and high-speed data storage systems.