數位信號處理器架構之功率消耗模擬

Abstract

在這篇論文中, 我們發表了一個可以接受不同層次硬體描述的功率模擬環 境. 它可以應用在線路模擬器所無法勝任的晶片層次設計.我們也提供電 壓調變及最長延遲路徑搜尋的功能, 來幫助設計者在滿足某一特定速度要 求下得到最低功率消耗的架構設計. 除此之外我們設計了兩個數位信號處 理器架構來確認此功率模擬環境的功能, 並顯示平行化對功率消耗的影 響.這些數位信號處理器架構是以 Verilog硬體描述語言來實現, 而我們 的功率模擬環境則與 Verilog-XL 邏輯模擬器完全相容. In this paper, we present a new power simulation envi- ronment which can accept the hierarchical descriptions. It is used for chip level designs which is too complex to use the circuit level simulator. We also provide functions of voltage scaling and critical path searching to obtain the lowest power architecture under a certain speed constraint. Besides, we designed two Digital Signal Processor architec- tures to confirm the functions of the power simulation envi- ronment and to show the effect of parallelism on the power consumption. The DSP architectures are implemented by Verilog Hardware Description Language and our power simulation environment is compatible with the Verilog-XL logic simulator.