标题: | 利用克霍诺神经网路的动态影像辨认系统之晶片设计 The Chip Design of Moving Object Recognition System with Kohonen Neural Network |
作者: | 徐永传 Yon-Chun Shie 吴重雨 Dr. Chung-Yu Wu 电子研究所 |
关键字: | 动态影像辨认; 克霍诺神经网路;Moving Object Recognition; Kohonen Neural Network (KNN) |
公开日期: | 1993 |
摘要: | 本论文提出了一个晶片组设计的动态影像辨认系统,我们可从一系列随时 间变动的影像资料中萃取出其中的运动物体,并加以分类辨认。由于二维 影像的资料量很大,若要对其做快速的运算,则平行处理的方式是最佳的 途径。本论文研制了二个具有平行处理能力的晶片,其中一个晶片适合萃 取动态影像,它是以1.0um BiCMOS 制程制造的。另一个晶片是以0.8um CMOS 制程制作的克霍诺神经网路,利用这个晶片我们可以组成一个具有 分类及辨认功能的阶层式克霍诺神经网路。同时, 为了因应更大的影像 资料, 这两个晶片可予以扩充连接成更大的网路。最后, HSPICE 的模 拟结果显示出我们的设计是正确的。 The chip design of a moving object recognition system is proposed. In this design, the moving object from a sequence of time-varying image data can be extracted and recognized as a membership grade of some class. Because of the large amount of data in the two-dimensional image, parallel processing is supposed to be the best candidate in solving this kind of problem. Two chips are designed in this thesis to realize parallel processing of image data. One is the prototype chip for moving object extraction and is fabricated by the BiCMOS 1.0um double poly double metal process technology. The other is the Kohonen neural network and is fabricated by the CMOS 0.8 um double poly double metal n-well process technology, which can be used to build a hierarchical Kohonen neural network for classification. Both of these two chips can be expanded to increase the size of image that can be processed. The HSPICE simulation results from these prototype chips have demonstrated the correctness in the design work and suc- cessfully verified the chip functions. |
URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT820430101 http://hdl.handle.net/11536/58106 |
显示于类别: | Thesis |