Title: 省電型 CMOS 單晶高壓產生器
Power-Efficient CMOS On-Chip High Voltage Generator
Authors: 陳曜洲
Isaac Y. Chen
吳介琮
Jei-Tsorng Wu
電子研究所
Keywords: 高壓產生器;High Voltage Generator
Issue Date: 1993
Abstract: 可攜式混合訊號系統之類比電路可以使用低電壓電源供應,藉以降低電路
之功率消耗,本論文提出一個電路架構,使類比電路可以在比 2伏特更低
的電壓供應環境下正常運作。低電壓類比電路須要特殊的訊號處理架構,
使電路之功率消耗達到最低,該電路包含全差動訊號路徑,其工作於兩個
低電壓電源線中,其中之類比開關控制須要一個單晶高壓產生器提供高壓
訊號,而不外接另一個高壓電源,藉以保證類比開關正常運作。為了使類
比開關正常運作,本論文提出一個單晶高壓產生器提供一個比晶片之電源
供應還要高的直流電壓源,以及一個時脈波形產生器用以控制類比開關,
類比開關須要高壓數位訊號,該高壓數位訊號之波形乃由時脈波形產生器
提供,而時脈波形產生器須要一個高壓電源供應,該高壓電源供應便由高
壓產生器產生。為了符合以上需求,本論文提出一個 1.2 伏特低功率
CMOS 類比至數位轉換器之開關控制與一個單晶高壓產生器。
Analog Circuits that can operate in a low supply voltage
environment are critical for portable mixed-mode systems. The
objective of this research is to investigate a circuits
techniques for analog CMOS integrated circuits so that they can
operate with a power supply voltage below 2 V. In order to
minimize power dissipation, a framework for low-power analog
signal processing is proposed. The framework contains a fully
differential signal path operating between two low-voltage
power rails, while analog switches are controlled by signals
with high voltage generated from a low-power on-chip high
voltage generator (HVG). A low-power on-chip high voltage
generator (CPG) and a clock pattern generator for control of
analog CMOS switches are under investigation. Low-power analog
CMOS switches require digital high-voltage control signals.
The digital high-voltage control signals have a supply voltage
above double Vdd to ensure analog CMOS switches at the adequate
ON state. In order to meet above specification, the efficient-
power CMOS on-chip high voltage generator and the analog
switches control for the 1.2 V CMOS analog-to-digital converter
(ADC) is studied.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT820430109
http://hdl.handle.net/11536/58116
Appears in Collections:Thesis