應用在動態影像預估的資料流導向平行架構設計

Abstract

本論文擬製作一顆以full search block matching motion estimation 演算法為基礎的晶片。為達到快速運算且100%硬體使用效率的目的，我們 在電路架構上採平行化的設計，並用較快速的電路來製作。應用在壓縮即 時影像資料上，Motion Estimation 是不可或缺的單元。簡單來說，本設 計可分為四個單元，包括記憶庫單元（Memory Bank Unit）、處理單元（ Processing Unit）、時間延遲單元（Delay Unit）及輸出單元（Output Unit）。記憶庫單元是用來儲存輸入的資料以備重覆使用，處理單元是做 search data 和reference data相減取絕對值加前一個PE（processing element）的結果，時間延遲單元有二個功能、儲存下一個reference data及將處理單元平行出來的結果diagonalize，使 timing正確，輸出單 元包括加法器和比較器，加法器將各個row distortion值相加，比較器則 把最小值找出來，把vector送出。在TSMC 0.8μm CMOS製程技術下模擬的 結果，該晶片時脈速度最高可達100MHz。這樣的結果意味著本晶片的發展 可以處理許多即時上的影像編碼。 In this thesis, a novel VLSI architecture is proposed for the implementation of the well-known full search block matching motion estimation algorithm. The architecture is based on efficient data flow design which allows sequential inputs but performs parallel processing to achieve 100% hardware efficiency. The architecture mainly consists of four units, namely memory bank unit, processing unit, delay unit and output unit. The memory bank unit stores input data in order to save data loading time. The processing unit does mean absolute difference between reference data and search data. The delay unit scales the output partial sum and stores the next reference data. The output unit adds every row distortion, identifies the minimum distortion among candidates, and then sends out the corresponding motion vector. Simulation results show that, based on TSMC 0.8μm CMOS process technology, clock speed up to 100MHz can be This implies that the developing chip can handle many video coding applications based on motion estimation method.