新型互補式金氧半差動邏輯電路之設計與分析及超大型積體電路之應用

Abstract

本論文提出幾個可應用於超大型積體電路之新型互補式金氧半差動邏輯電 路。首先提出新型動態三進位邏輯電路，又提出簡易三進位差動邏輯及其 設計步驟。又提出新型三進位邏輯系統的設計方法及電路。鉗位差動邏輯 其內部為電流訊號，經由傳統靜態反向器轉換為電壓訊號，與傳統邏輯電 路相容。鉗位差動邏輯可將複雜布林函數製作於一個邏輯閘中，不只增快 速，而且減小功率延遲乘積。自控時脈式差動鎖存器及其改良型電路、鎖 存式差動邏輯及其改良型電路、與鎖存式傳送電晶體差動邏輯及其改良型 電路，均應用在真單相時脈管流系統，其對時脈斜度不敏感，所需求時脈 緩衝器容易設計，負載減小，因此，產生的電源雜訊大大減小，更適用於 高速超大型積體電路之系統設計。本論文提出之新型電路，均可應用於高 速超大型積體電路，經由實驗晶片之設計、製作、及測量，新電路的部分 特性得以驗正。最後，利用乘法器及加法器之設計作為應用說明，更可以 看出這些新型電路之實用優點。適當的應用不同邏輯電路，可提高系統之 性能最佳化，所以在高速超大型積體電路系統中，具有高度的應用及發展 潛力。 In this thesis, two new dynamic CMOS ternary differential logic circuits are proposed and analyzed. New dynamic CMOS ternary logic circuits and design methodology can be used to increase the packing density and interconnections. New static differential logic circuit with internal current signal allows a complex function implemented within a single gate to achieve high-speed operation and low power-delay product. Several new differential latches and logic circuits for the true-single- phase pipined systems are clock slope insensitive. The clock loading can be reduced and the clock drivers can be simplified. Both circuit performance and design flexibility can be further improved. New binary multipliers are designed by using the proposed dynamic ternary logic circuits in the interior part. Various true-single-phase pipelined multipliers are designed with the new differential latches and logic circuits. Experimental chips of the proposed new logic circuits have been designed and fabricated. The measured results are consistent with SPICE simulation results.