雙址脈波調位直接序列中的判定指引同相式延遲鎖相追蹤迴路

Abstract

本論文中我們參考判定指引同相式延遲鎖相迴路(Coherent decision- directed delay-lock tracking loop,CDD-DLL)的架構，用以發展雙址脈 波調位直接序列(Binary pulse-position modulated direct sequence, BPPDS)之分碼多重存取(CDMA)系統中的追蹤迴路。此追蹤迴路，不但保持 原有系統的特性如：（一）可節省發射能量，（二）對交互相關雜訊( Cross-correlation noise)有優異的壓抑性，（三）對白雜訊(White noise)有能量衰低效應(Power reduction effect)之外，而且還有元件平 衡(Component balance)及簡化硬體線路的優點。在本文中我們特別強調 交互關聯雜訊對追蹤迴路的影嚮。文中分別討論迴路錯誤特性(Loop error characteristic)，追蹤擾動(Tracking jitter)及平均鎖相失效的 時間(Mean time to lose lock)的性質。由數值分析得知：所建議的系統 比傳統的BPSK-DS-CDD-DLL迴路系統，不論在追蹤擾動或平均鎖相失效時 間上，都有大約5dB的增益。 In this thesis the coherent decision-directed delay-lock tracking loop(CDD-DLL) scheme is employed to develop a tracking loop for the binary pulse-position modulated direct sequence( BPPDS) CDMA system. It not only keeps the of BPPDS-CDMA system which has transmitting energy saving, a superior suppression of cross-correlation noise(CCN) and a significant spreading effect on white noise, but also has of components balance and hardware simplicity. In this proposed CDD-DLL of BPPDS system, the influence of CCN is emphasized. The normalized loop error characteristic (NEC),steady state tracking jitter, and mean time to first lock loss are discussed and presented. The numerical results show that there is approximately a $5dB$ gain in both normalized tracking jitter variance and normalized mean time to lose lock as compared to the conventional CDD-DLL of BPSK-DS system.