對具一致性快取記憶體叢集多重處理機之模擬研究

Abstract

本篇論文利用現有的 SCI 一致性規約配合匯流排 Write-Once 一致性規 約，設計一叢集架構下的一致性規約，並將之實現於 PROTEUS 模擬器上 。並將利用此模擬環境探討叢集架構之優劣。發現：在對記憶體負荷較大 的程式中，以叢集架構系統效能最好。此乃因匯流排無法解決大量的記憶 體存取碰撞，而網路系統在處理機數目太多時使網路尺寸太大而造成傳輸 時間太長。至於那些對記憶體系統負荷較小的程式而言，叢集系統之表現 僅次於匯流排系統。此乃由於匯流排之頻寬 (bandwidth) 已能夠應付標 竿程式之需要，故其效能以匯流排系統較佳，叢集次之；但因匯流排之限 制使得系統不允許太多處理機連接於上，是故叢集系統是為未來多處理機 系統較佳之選擇。這些結果可提供系統設計者作為重要之參考。 In this thesis, we have designed a cache coherence protocol combining the nowaday existing SCI with Write-Once protocol for the clustered architecture, and implement it on the PROTEUS system. We also use it to evaluate the performance of the cluster and find that the performance of the cluster is the best on heavily memory loaded benchmarks. Because the bus can not well service a large number of access contentions, the performance of a bus system is worse than that of the cluster. The network system works worse than cluster with a large number of processors due to the long memory access latency through the large interconnection network. For those lightly memory loaded benchmarks, the bus system works best. It is because the bandwidth of the bus can easily meet the requirements of memory accesses. The cluster system works better than the network system because of the smaller size of interconnection network. These important results can be referred to the system designers.