完整後設資料紀錄
DC 欄位語言
dc.contributor.author田博仁en_US
dc.contributor.authorBor-Zen Tienen_US
dc.contributor.author吳慶源en_US
dc.contributor.authorChing-Yuan Wuen_US
dc.date.accessioned2014-12-12T02:13:43Z-
dc.date.available2014-12-12T02:13:43Z-
dc.date.issued1994en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT830430039en_US
dc.identifier.urihttp://hdl.handle.net/11536/59226-
dc.description.abstract本文將詳盡地分析與探討由熱載子所引起的元件衰退現象. 實驗中所選用 的元件為傳統式之 NMOS與 PMOS. 藉由比較性分析,我們可將 Oxide traps 及 interface states 所產生的效應區分開. 在過去, 由熱載子應 力所引起的臨界電壓改變 ( threshold-voltage shift ) 都以一簡單的 時間冪次方公式 ( simple power law ) 來預測。 為了要檢驗此一簡單 的統計公式是否真的能適用於所有的情況 , 我們將元件置於更長時間的 直流應力之下, 並分析結果. 文中將指出當應力時間加長, 此一時間冪次 方關係式並無法正確的預測出由 interface states 所導致的臨界電壓改 變量! 而由 Oxide traps 所導致的臨界電壓改變量則可很概略的被估計 出來。 In this papers, a detailed study on hot-carrier-induced device degradation is made and analyzed. The devices involved in this study were conventional N-MOSFET's and P-MOSFET's. A comparative study of device degradation is presented to distinguish the effects of oxide traps from interface-state generation. In the past, hot-carrier-induced threshold-voltage was fitted by a simple power law. We examine this empirical model by using a much longer time stress. It is shown that this power law relationship is invalid for the case of interface- stat -es generation and is valid for the case of oxide-trapped charge .zh_TW
dc.language.isoen_USen_US
dc.subject熱載子效應; 界面陷阱; 臨界電壓偏移。zh_TW
dc.subjectHot carrier effect; Interface trap; Threshold-voltage shift.en_US
dc.title超大型CMOS元件在直流應力下之熱載子衰退現象zh_TW
dc.titleHot-Carrier Degradation Behaviors of VLSI CMOS Devices Under DC Stressesen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
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