使用於低電源電壓互補式金氧半數位電路之背閘順偏技巧

Abstract

近來，由於主要由電池為電源的攜帶式筆記型個人電腦及通訊設備已 日漸普及，因此具有低功率消耗優點的大型積體電路也日益重要。然而所 面臨的問題是，為了實現低功率消耗操作供應電壓必須降低。同時，為了 滿足較高的操作速度臨界電壓必須被調低，因此我們必須使用較低的通道 攙雜濃度。如此卻增加了短通道效應，並且較低的臨界電壓將造成較大的 預備電流。基於以上所述，我們期待一個可調變的臨界電壓應用在金氧半 場效電晶體上，也就是說在主動模式時臨界電壓降低以提供較高的驅動電 流，而預備模式時臨界電壓提升以大量抑制預備狀態時的靜態功率散逸。 為了滿足這個要求，背閘極順偏結構在此將被仔細的討論。本論文中提出 了一個可動態提供背閘極順偏，以提高低電壓互補式金氧半數位電路操作 速度的結構，其中包括理論的整理、實驗及模型。 Recently,low-power LSIs have become increasingly important because of the spread of battery-operated portable computers and communication equipment. It is essential to reduce the supply voltage (VDD) in order to realize low-power CMOS, along with the threshold voltage (Vth) lowered in order to maintain high operation speed. A low channel impurity concentration for Vth reduction, however, not only increases the short channel effect but also causes a large standby leakage current. Therefore, a dynamic threshold voltage for MOSFET is expected, i.e., in the active mode the threshold voltage is reduced such as to offer higher drive current, while the threshold voltage is maintained at a high value in the standby mode and the standby power is reduced exponentially. To meet this requirement, here a scheme of forward biasing the back gate or bulk-to-source junction of MOSFET is extensively investigated. This thesis includes the theory, the experiment, and the modeling work all concerning the scheme of providing a dynamic forward bias for enhanced speed in low supply-voltage CMOS digital circuits.