化學機械研磨平坦化技術應用於積體電路之研究

Abstract

在 VLSI 中, 元件尺寸越做越小時, 多層金屬層及平坦化成為不可或缺的 技術, 平坦化是為了景深 (Depth of Focus) 的問題所衍生出來的, 而化 學機械研磨 CMP(Chemical Mechanical Polish)是提供全面性(Global)平 坦化的唯一技術, 在這一研究中, 首先對 CMP 的特性作分析,然後以 UMC (聯華電子) 0.6μｍ CMOS 的產品以 SOG (Spin on Glass) 和 CMP 兩種製程做比較, 結果顯示在不會影響 MOS 元件特性之情況下,CMP 技術 可以得到較佳的平坦化。 As VSLI devices are scaled down to ever smaller dimen- tion. The chip size is not only getting smaller but also actually increasing in quantity for each device generation. Then multilayer of metallization is needed. Requirements for local and global planarization become more stringent as a result of the increased numerical aperture and reduced depth of focus (DOF) in deep submicro lithography. Although numerous traditional planarization technologies are available. Chemical mechanical polishing (CMP) is the only technology known to provide global plana- rization of topography with low post-planarization slope work on dielectric planarization. In this work, we offer basic characteristics of CMP with two different dielectrics no pattern test wafer. The results indicate that polishing rate varies with parameters of CMP. And we compare CMP with SOG planarization techniques by practicing UMC double metal 0.6μm product. The result shows that CMP get flatter, and it does not affect characteristics of the MOS devices after CMP.