寄生在CMOS中之BJT的特性分析與模式

Abstract

近年來標準金氧半電晶體技術之寄生雙載子接面電晶體受到工業界與學術 界相當大的重視, 此類元件已被應用於數位與類比整合電路中(例如: bandgap voltage reference circuit, low-noise amplifier etc. ) 它 之所以被重視與應用, 乃在於其較低之製造成本與成熟的製造技術.在本 篇論文中, 我們實際製作並且量測一CMOS技術中之橫向雜散雙極性電晶體 的特性, 此電晶體可直接應用於CMOS數位電路中. 我們並導出一公式研究 元件的電流增益與佈局的幾何關係. 經調整layout geometry後,我們 以0.8umCMOS 製程達到Beta接近30左右.我們亦建立一套全自動元件特性 量測與參數萃取系統, 此係統是以套裝商業軟體Aurora為基礎. 在雜散縱 向電晶體中, 模型與實驗可得到一致的表現, 然而在雜散橫向電晶體中, 模擬值只有在主動區域內才與實際量測值穩合, 但在飽和區域內卻有相當 大的差異, 主要原因是橫向電晶體與縱向電晶體是共同存在而產生的, 此 縱向電晶體很明顯的影響橫向電晶體在飽和區域的特性, 為了解決此一問 題, 我們提出了三個串聯電晶體之元件模型, 我們並且發展一特殊的量測 與萃取方法, 此一方法的準確度經與實驗值比對後已被證明. In this thesis, lateral parasitic BJT's in the standard CMOS technology were characterized and modeled. An analytical expression was derived to study the layout geometric effects on the performance of the lateral BJT's.A current gain of nearly 30 has been achieved in a 0.8um CMOS process process by optimizing the layout geometry. A fully automatic device characterization and parameter extraction system which is based on a commercial software tool Aurora has been set up. A good agreement between measurement and SPICE modeling is achievable with Aurora for the parasitic vertical BJT's. With respect to the lateral BJT's, a good match is obtained only in the active region. In the saturation region of the BJT's, a large discrepancy is obtained due to the contemporary existence of the parasitic vertical BJT's. To resolve this problem, a three series BJT's model was proposed. A special measurement and parameter extraction technique was also developed to separately extract the three BJT parameters. Such a model has been verified by a favorable comparison of the I-V characteristics between the SPICE simulation and measurement.