鎢閘極金氧半結構採新製程之特性研究

Abstract

採用鎢閘極金氧半互補式電晶體，有兩項優點：第一，金屬功函數在矽能 階之中點，故臨限電壓不需調整；第二，可降低RC延遲時間，提高交換速 度。基於這兩項優點，本論文主要在探討採用新製程，來建造－鎢閘極金 氧半結構。我們在閘極氧化層鍍上一層薄複晶矽，以備CVD-W成長鎢閘極 時之消耗。由我們的實驗可知，大約250埃複晶矽層被消耗。因此，預備 250埃之複晶矽膜於閘極氧化層，我們可以建造出一純鎢閘極金氧半結構 。與濺鍍法所建造之鎢閘極金氧半結構做一比較，發現除了崩潰電壓稍差 外，其餘電性例如片電阻；崩潰電荷；介面缺陷密度和氧化層強度等，均 為採用新製程方法所得者為佳。 The W-gate CMOS devices possess two major advantages. The first advantage is that the workfunction of tungsten results in the alignment of metal Fermi level to the mid bandgap of Si substrate. Therefore, there is no need to adjust the devices' threshold voltage. The second advantage is that the low resistance W-gate, as compared to the high resistance polysilicon gate, can reduce the RC delay time and thus enhance the speed of switch. Based on this consideration, a new process was developed for the W-gate MOS capacitor using the technique of selective CVD-W. In this process, a thin sacrificial layer of poly-Si with an appropriate thickness is first deposited on the gate oxide, and is to be consumed by the subsequent CVD-W deposition. Compared with the sputter deposited W-gate MOS capacitor, the CVD-W gate MOS capacitor has a lower sheet resistance (Rs), larger charge to breakdown (Qbd), lower interface state density (Dit) except a slightly lower breakdown field. Various evidences shows that the new CVD-W gate process is a useful and promising technique.