低功率絕熱邏輯電路

Abstract

絕熱式交遞與電荷循環使用為兩種降低功率消耗之新方法：藉由絕熱式交 遞之技術，在能量轉移週期 T 遠大於線路時間常數 RC 情況下，由於動 態充放電所產生於電阻性元件上之熱能耗損將可望降低。 若採取電荷循 環使用之機制，儲存於電容負載之能量流失將可恢復並於後續週期中再被 使用。本論文中，我們提出一個新的脈衝式電壓源交錯差動邏輯 (PPS- CCDL)，其整合了絕熱差動邏輯閘與閘閂元件。與先前被提出 PPS-CMOS 比較 ，由於去除了複雜之 PMOS trees 與不必要之 glitch和 transition，PPS-CCDL 可由公式與模擬來證明所耗損的功率較 PPS- CMOS 為低。同時，由於 PPS-CCDL 之脈衝式電壓源有較小且與資料無關 之電容負載， 整個系統之也將節省較多之能量耗損。我們使用標準之 0.8um CMOS 製程實做了一個八位元管線化加法器，目前於測試中。另外 也設計了一顆應用晶片, PPS/static 23-bit correlator with 8-bit I/ O, 並已交付送審製作。 Adiabatic Switching and Charge Recycling are two new techniques to reduce power consumption: with the Adiabatic Switching technique, heat dissipation on resistive device channels caused by dynamic charging and discharging is reduced if energy transfer period T >> RC, where RC is the time constant of the circuit. Exploiting the Charge Recycling technique, loss of stored energy in capacitive loads can be recovered for reuse in subsequent cycles. In this paper, we propose a new logic family - Pulsed Power Supply Cross-Coupled Differential Logic (PPS- CCDL), which integrates the adiabatic differential logic gate and a latch. PPS-CCDL can be shown througth derivations and simulations to dissipate less power than the previously proposed PPS-CMOS approach, by eliminating the PMOS trees and the unnecessary signal glitches and transitions in PPS-CMOS. A higher power saving of the overall system is anticipated since PPS-CCDL presents a smaller and data-independent capacitive loads to the pulsed power supply. We implemented an 8-bit pipelined adder with a 0.8um standard CMOS technology, which is under testing. Another application chip of PPS/static 23-bit correlator with 8-bit I/O was submitted to CIC for fabrication.