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dc.contributor.author林志勇en_US
dc.contributor.authorChich-Yung Linen_US
dc.contributor.author沈文仁en_US
dc.contributor.authorWen-Zen Shenen_US
dc.date.accessioned2014-12-12T02:13:51Z-
dc.date.available2014-12-12T02:13:51Z-
dc.date.issued1994en_US
dc.identifier.urihttp://140.113.39.130/cdrfb3/record/nctu/#NT830430127en_US
dc.identifier.urihttp://hdl.handle.net/11536/59322-
dc.description.abstract數位訊號處理的應用近年來已大幅成長, 舉凡在語音訊號、影像、視頻傳 輸、雷達、醫學電子等各方面都已逐漸取代傳統類比訊號處理的地位。而 在這些數位訊號處理的應用中, 離散傅利葉轉換 (DFT) 一直扮演著極重 要角色, 例如頻譜分析、數位濾波器設計等都可用離散傅利葉轉換來完成 。但因離散傅利葉轉換的運算複雜度高, 且在大部分的實際應用上,我們 所要處理的點數都很長, 因此完成一個離散傅利葉轉換需要極大的運算量 。有鑑於此, 我們設計一個可替換離散傅利葉轉換的處理方法─離散哈特 萊轉換 (Discrete Hartley Transform, DHT)。在本篇論文中, 我們設計 出一個可實現一千零八點連續輸入實數的高速離散哈特萊轉換模組。我們 採用由固德與湯瑪斯 (Good -Thomas) 所提出的質因數演算法則配合中國 餘數定理, 把一維長點數的離散哈特萊轉換映成三維短點數的方式來處理 。對於短點數的轉換, 我們使用了分散式運算的觀念與唯讀記憶體--累加 器的架構來完成, 如此可以有效的降低系統的運算複雜度, 並且節省了許 多硬體花費。我們的離散哈特萊轉換系統可以工作在25兆赫芝的頻率, 而 且處理一千零八點連續輸入實數的離散哈特萊轉換僅需40.3奈秒。我們的 架構的主要好處是處理速度快, 而且在不影響速度的前提下, 選擇了最適 合用超大型積體電路實現的演算法則與硬體架構, 儘量使面積變小。我們 採用Verilog 模擬器來進行硬體設計, 並將其映至台灣積體電路公司 (TSMC) 的0.8 微米標準元件庫。 The applications of digital signal processing is widely increaed these years. There are many applications,such as video, image, speech, radar, medical electronics, etc., and it has become a substitute to traditional analog signal processing. In all these applications, the discrete Fourier transform (DFT) plays an important role.In practical applications, the transform length is very long. The complexity of computating DFT becomes more serious as the transform length getting longer. For this reason, we introduced the discrete Hartley transform (DHT) which is another method for digital signal processing. In this thesis, we propose a discrete Hartley transform for digital signal processing. To reduce the hardware cost, we use the Good-Thomas prime factor algorithm. Combining with the Chinese remainder theorem, we can map a one-dimensional long length DHT into three-dimensional short length DHT. Using distributed arithmetic concept and ROM-accumulator architecture, we implement a 1008 DHT for continuous real number input data. This system can work at 25 MHz clock rate and it needs only 40.3u sec to perform 1008 points DHT. The main merit of our architecture is high speed.zh_TW
dc.language.isoen_USen_US
dc.subject離散哈特萊轉換; 質因數演算法則; 中國餘數定理.zh_TW
dc.subjectDHT; Prime Factor Algorithm; Chinese Remainder Theorem.en_US
dc.title應用於數位訊號處理之離散哈特萊轉換的設計與實現zh_TW
dc.titleDesign and Implementation of Discrete Hartley Transform for Digital Signal Processingen_US
dc.typeThesisen_US
dc.contributor.department電子研究所zh_TW
Appears in Collections:Thesis