标题: 快速之座标旋转演算法处理器设计
Implementation of Redundant CORDIC Processor with Efficent Variable Scale Factor Compensation
作者: 黄焯熙
Jurcy Hwang
陈绍基
Sau-Gee Chen
电子研究所
关键字: On-line 比例因数分解; 座标旋转演算法;On-line scale factor decomposition; CORDIC
公开日期: 1994
摘要: CORDIC演算法为许多基本数学运算提供了快速的计算方式。在本篇论 中
,我们提出了以on-line 的方式与座标及角度运算同步计算比例因数
scaling factor )分解的 Radix-2 Redundant CORDIC 架构以解决此顐
狾]数数必须保持为常数的困扰。比例因数的分解乃藉由计算指数函数漱
颓k求得的,将比例因数分解成Σln(l+s*2^(-i))(radix-2)并以检查怜
玫X位元来简单估计 s,如此我们可以简单快速且小面积的电路计算之A方
向参数的计计亦同。在比例因数补偿方面我们提出三种方法:ヾ在所釭漕
井蚺峸y标算算结束之后再做移位和加法的运算;ゝ每个递回运算结纁犮
艅韐N做移位和加法的运算;ゞ将比例因数 on-line计算出来并且在井蚺
峸y标运算结束后以乘法器完成计算。另外由于比例因数可以是变数A我们
将此 Radix-2 Redundant CORDIC 演算法推展至 Radix-4 以减少挚j运
算的次数及加速 CORDIC 的运算和减低成本。最后我们以新的演算k为基
础使用 CCL standard cell与CADENCE's tool设计了radix-2 的旋鉏狾★
q路,并送至 CIC 制成晶片,此晶片速度33MHz,约有9000个逻辑h,面积
约为5120μmx 4740μm。
In this work, an efficient variable scale factor compensation
for the redundant CORDIC is discussed. The compensation scheme
transforms the complicated variable scale factor problem
introduced in using redundant CORDIC into a sequence of simple
shift-and-add operations. The resulted CORDIC enjoys both fast
speed in rotation iteration as well as high speed and low
overhead scale factor compensation which is difficult for
existing redundant CORDICs. With the on-line variable scale
factor decomposition, we discuss three scale factor
compensation schemes which are tailored for better cost/
performance consideration for different hardware realization
strategies. We also extend the radix-2 redundant CORDIC and
variable scale factor compensation algorithms to a radix-4
version for better speed and area performance consideration.
Finally the algorithm is VLSI implemented as a rotation-mode
CORDIC processor by using CCL standard cells and CADENCE's
tools. The CORDIC chip layout has been sent to CIC for chip
realization. The chip has a 33MHz clock rate, 9000 gates, and a
area of 5142um x 4123um.
URI: http://140.113.39.130/cdrfb3/record/nctu/#NT830430139
http://hdl.handle.net/11536/59337
显示于类别:Thesis