在聚集晶元佈局上K-方電路分割,擺置改良,區域定義和繞線順序設計之設計

完整後設資料紀錄

DC 欄位	值	語言
dc.contributor.author	顏金泰	en_US
dc.contributor.author	Yan, Jin Tai	en_US
dc.contributor.author	蕭培墉	en_US
dc.contributor.author	Xiao, Pei Yong	en_US
dc.date.accessioned	2014-12-12T02:14:17Z	-
dc.date.available	2014-12-12T02:14:17Z	-
dc.date.issued	1994	en_US
dc.identifier.uri	http://140.113.39.130/cdrfb3/record/nctu/#NT832394003	en_US
dc.identifier.uri	http://hdl.handle.net/11536/59765	-
dc.language.iso	en_US	en_US
dc.title	在聚集晶元佈局上K-方電路分割,擺置改良,區域定義和繞線順序設計之設計	zh_TW
dc.title	The design of K-way circuit partitioning, placement refinement, region definition and routing ordering assignment in macro cell layout	en_US
dc.type	Thesis	en_US
dc.contributor.department	資訊科學與工程研究所	zh_TW
顯示於類別：	畢業論文