非晶矽薄膜電晶體之銅閘極製程與氧化矽閘極介電層之特性研究

Abstract

本文利用低阻值銅/鈦化鎢雙層金屬閘極製妨晶矽薄膜電晶體閘極製 作非晶矽薄膜電晶體,並以電漿輔助化學氣相沈積法研製氧化矽介電層非 晶矽薄膜體,以試圖改進薄膜電晶體的電可靠性. 以低阻值/鈦化鎢雙 層金屬閘極製作之非晶矽薄膜電晶體薄膜電晶體,可以有效降低閘極線路 中的訊號延遲問題,並避免掉鋁閘極製程中丘狀突起和鬚狀物的產生.在銅 閘極的製作,我們以濕式化學蝕刻的方法,採用不同的蝕刻液選擇性的蝕刻 銅和鈦化鎢.銅的蝕刻液是以大量醋酸稀釋鋁蝕刻液,藉由調變不同醋酸和 鋁蝕刻液配比蝕刻銅膜,發現醋酸含量在70-80%之蝕刻液,有較佳的蝕刻均 勻性和低的側向蝕刻.並且得到形狀極佳的閘極橫截面,可確保製程的可靠 度.以此銅閘極所製作之薄膜電晶體,具有高載子移動率(0.8cm2/V.s),低 次臨界漂移(0.24V/dec.)和1.2V的低啟動電壓. 另外,本文亦製作矽烷 和TEOS為氣體 源的氧化矽介電層薄膜電晶體,討論氧化矽介電層對於非晶 矽薄膜電晶體特性之關係.發現具較少量氫相關鍵結和電漿相關缺陷的氧 化層有較佳的電性和可靠度.氧化矽薄膜電晶體的不穩定因素,主要來自於 氧化矽中的缺陷和介面區域的位階增量.元件在電場的作用下,促使氧化矽 中的弱鍵斷裂成為一懸鍵與一氫鍵而形成一缺陷陷阱,抓取電子成為固定 電荷,致使啟動電壓的漂移.此一反應機制與氫原子的移動有關,氫含量較 少的氧化矽薄膜有較緊密的結構和良好的穩定性,以其製做之薄膜電晶體 具較佳的電可靠度.另一方面,氧含量高的氧化矽膜和非晶矽薄膜介面卻因 氧原子具高電負度使介面矽鍵強度變弱,增加介面產生位階增量的機率. 最後,我們以化學退火的方法嘗試製作具化學退火非晶矽半導體層之薄膜 電晶體,希望可以得到較佳之可靠度.實驗發現經化學退火後之試片其載子 移動率明顯降低,而在電應力偏壓量測,當閘極偏壓超過20V時,其次臨界漂 移停止上升,而載子移動率明顯提升.可能是由於化學退火後之非晶矽中隱 藏的大量應變弱鍵遭激發載子打斷,進而釋放非晶矽中之應力,減少尾態能 帶寬度,導致載子移動率的提升. In this thesis we used low resistivity Cu/TiW double layered gate metal fabrication a-Si:H THT.Using low resistivity Cu metal as gate can effectively reduce RC delay in gate line and at the same time prevent the production of hillocks and whisker.In this way,Cu/TiW gate utilizes a complete chemical wet etching process.While Cu etched by various ratio of CH3COOH and Al etchant,we find that CH3COOH 70~80% buffer Aletchant have a uniform etching morphology,small side etch distance and excellent taper shape.The TFT with Cu/TiW double-layered gate metal provides good electrical performance,such as the small threshold voltage(1.2V),low subthreshold swing(0.24V/dec.) and high mobility (0.8cm^2/V.s). SiH4-N2O based and TEOS-O2 based oxide are fabricated in a-Si:H TFT as gate dielectric to investigate the oxide gate dielectric properties on the a-Si:H TFT performance.We find that PE-TEOS oxide have better step coverage than silane-based oxide and the surface of PE-TEOS oxideis more smooth.The breakdown strength for TEOS oxide is 8.5 MV/cm and 8 MV/cm for silane-based oxide.The value have high enough for TFT device.Both have been used a TFTs gate dielectric,and the best electrical performance is Vth about 5V, S=0.4 V/dec.,and ufe=0.6cm^2/V.s.The TFTs electrical performance with silane-based oxide are improved accompanying with oxide properties that with fewer hydrogen related bonds and rigid structure.The Vth shift decrease with the oxide gate insulator that with fewer hydrogenrelated bonds.But the subthreshold swing shift shows an inverted tendency that may resulting from the interface bonding structure related to O atoms induced weak silicon bond structure.The TFTs electrical performance with TEOS-based oxide gate insulator have similar result that oxide with complete Si-O bonding has better performance.But the oxide deposited under high power will producing a large amount of fixed charge trap in oxide by plasmadamage and resulting in high threshold voltage. SiNx TFTs with CA a-Si:H and H2 plasma treatment SiNx surface TFTs have been prepare.CA a-Si:H TFTs have many interface layers in a-Si:H and more interface states are build up resulting in decrease in ufe and increase in S.When gate bias is applied,the S will reach a saturation value and ufe will increase.The reson still not clear,maybe cause by the release of the strain in a-Si:H.from breaking weak bonds for H2 plasma treatment SiNx surface TFT when gate bias is performed both S and mobility decrease.Because the plasma damage the interface,an unstable interface is produced.All the sample have worse electrical properties than conventional SiNx TFTs.The instablity in oxide gate dielectric a-Si:H THT mainly come from the trap defect centers in oxide and state creation at or near the interface.